公开(公告)号：US6081848A

公开(公告)日：2000-06-27

申请号：US134737

申请日：1998-08-14

申请人： Paul A. Grun ,  William Futral

发明人： Paul A. Grun ,  William Futral

IPC分类号： G06F13/12 ,  H04L12/56 ,  G06F3/00 ,  G06F13/00

CPC分类号： H04L49/901 ,  G06F13/128 ,  H04L49/90 ,  Y10S370/912

摘要： An I/O unit for transporting a data block having a plurality of data packets across an interconnect includes an I/O controller and a memory coupled to the I/O controller for storing the data block. The I/O unit further includes a DMA object created by the controller and referring to the data block, and a transport that has a first and second VI queue pair, with each queue pair being coupled to the interconnect. The I/O unit further includes a first descriptor created by the transport and referring to a first data packet, and a second descriptor created by the transport and referring to a second data packet.

摘要翻译： 用于通过互连传输具有多个数据分组的数据块的I / O单元包括I / O控制器和耦合到I / O控制器的存储数据块的存储器。 I / O单元还包括由控制器创建并参考数据块的DMA对象以及具有第一和第二VI队列对的传输，每个队列对被耦合到互连。 I / O单元还包括由传输器创建并引用第一数据分组的第一描述符和由传输器创建并参考第二数据分组的第二描述符。

公开(公告)号：US5713044A

公开(公告)日：1998-01-27

申请号：US575663

申请日：1995-12-19

申请人： Byron Gillespie ,  Elliot Garbus ,  William Futral

发明人： Byron Gillespie ,  Elliot Garbus ,  William Futral

IPC分类号： G06F13/28 ,  G06F15/02

CPC分类号： G06F13/28

摘要： Dynamic appending of chain descriptors is described with reference to a computer system having a host processor, a DMA unit, a host memory and an external memory wherein the DMA unit controls transference of data between the host memory and the external memory based upon data transference parameters specified in chain descriptors created by the host processor and stored as data structures within the host memory. In accordance with one method and apparatus described herein, dynamic appending of chain descriptors is achieved by employing a resume bit stored within a register of the DMA unit. The host processor, upon creating a new group of chain descriptors to be appended to a previous group, updates a link value within a last chain descriptor of the previous group to point to the first chain descriptor of the new group and also sets the resume bit within the DMA unit. The DMA unit reads chain descriptor parameters, including link values, they perform a data transfer operation specified by the chain descriptor parameters. Upon completion of the transfer operation, the DMA unit examines the resume bit and, if set, the DMA unit rereads the link value for the current chain descriptor. If the resume bit has not been reset, the DMA unit merely proceeds to process the next chain descriptor specified by the previously read link value or, if that link value is a null value, the DMA unit merely terminates operation. In an alternative embodiment described herein, the host processor updates link values but does not set a resume bit within the DMA unit. Rather, the DMA unit initially reads all parameters for a chain descriptor except for the link value. Then, after completion of the data transfer operation specified by the chain descriptor, the data unit reaccesses the chain descriptor to read the link value. Hence, if the link value is updated by the host processor while the DMA unit is processing a chain descriptor, the DMA unit will nevertheless access the updated link value upon completion of the data transference operation. Method and apparatus embodiments are described herein.

公开(公告)号：US20060136611A1

公开(公告)日：2006-06-22

申请号：US10750060

申请日：2003-12-30

申请人： William Futral ,  Kenneth Creta ,  Sujoy Sen ,  Gregory Cummings ,  Sivakumar Radhakrishnan

发明人： William Futral ,  Kenneth Creta ,  Sujoy Sen ,  Gregory Cummings ,  Sivakumar Radhakrishnan

IPC分类号： G06F13/28

CPC分类号： G06F13/4027

摘要： Apparatus and method for a first device to query a second device for the availability of a hardware feature within the second device, and for the second to receive and analyze the query to determine whether or not to respond, depending on the version of hardware feature sought, a code identifying a vendor, etc., and responding with a reply providing an indication of availability of the hardware feature and/or an address at which the hardware feature may be accessed, if the determination is made to reply.

摘要翻译： 用于第一设备的第二设备查询第二设备内的硬件特征的可用性的装置和方法，以及第二设备接收和分析查询以确定是否响应，取决于所寻求的硬件特征的版本 ，识别供应商等的代码，并且如果确定作出回复，则响应提供硬件特征的可用性的指示和/或可以访问硬件特征的地址。

公开(公告)号：US07007126B2

公开(公告)日：2006-02-28

申请号：US09023494

申请日：1998-02-13

申请人： Byron R. Gillespie ,  Barry R. Davis ,  William Futral

发明人： Byron R. Gillespie ,  Barry R. Davis ,  William Futral

IPC分类号： G06F13/38

CPC分类号： G06F13/404 ,  G06F12/0284

摘要： An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range. In a particular embodiment, the I/O subsystem may be implemented as a single integrated circuit chip (I/O processor) which is configured to support the intelligent I/O (I2O®) protocol in connection with Peripheral Components Interconnect (PCI) primary and secondary system busses. By configuring the bridge to claim the MU address range on the secondary bus, the I/O subsystem may permit agents on the secondary bus to perform the I2O protocol without interrupting the host processor which normally resides on the primary PCI bus.

摘要翻译： 具有处理器，桥接单元和将计算机系统中的主要，次要和第三总线耦合的I / O消息单元的I / O子系统。 桥单元可配置为声明从辅助总线访问消息单元（MU）地址范围的请求，MU本身耦合到主总线。 当发出I / O请求时，MU中断处理器，响应处理器从MU指针读取到I / O消息，然后可以执行I / O消息。 为了促进在希望访问MU的主总线或辅助总线上为代理编写的软件的可移植性，I / O子系统的主地址转换单元和辅助地址转换单元被编程为要求相同的地址转换窗口，其中MU 地址范围是主ATU地址转换窗口的一部分，并且辅助ATU被配置为不在MU地址范围内要求请求。 在特定实施例中，I / O子系统可以被实现为单个集成电路芯片（I / O处理器），其被配置为支持智能I / O（I 2 O） 协议与外围组件互连（PCI）主要和次要系统总线相关。 通过配置桥接器要求辅助总线上的MU地址范围，I / O子系统可以允许辅助总线上的代理执行I＆lt; 2＆gt; O协议，而不中断通常驻留在主机处理器 主PCI总线。

公开(公告)号：US20060136639A1

公开(公告)日：2006-06-22

申请号：US11020500

申请日：2004-12-21

申请人： William Futral ,  Kenneth Creta ,  Sujoy Sen ,  Gregory Cummings ,  Sivakumar Radhakrishnan

发明人： William Futral ,  Kenneth Creta ,  Sujoy Sen ,  Gregory Cummings ,  Sivakumar Radhakrishnan

IPC分类号： G06F13/14

CPC分类号： G06F13/4291

摘要： A system, method and apparatus for prioritizing transactions is disclosed. I/O devices may generate transactions with a stream identifier. A transaction classifier may assign a priority to a transaction based upon a stream identifier of the transaction. An arbiter may select a transaction for processing based upon priorities assigned to the transaction.

公开(公告)号：US20060095609A1

公开(公告)日：2006-05-04

申请号：US10977235

申请日：2004-10-29

申请人： Sivakumar Radhakrishnan ,  Siva Balasubramanian ,  William Futral ,  Sujoy Sen ,  Gregory Cummings ,  Kenneth Creta ,  David Lee

发明人： Sivakumar Radhakrishnan ,  Siva Balasubramanian ,  William Futral ,  Sujoy Sen ,  Gregory Cummings ,  Kenneth Creta ,  David Lee

IPC分类号： G06F5/00

CPC分类号： G06F13/1631 ,  G06F12/0831 ,  G06F12/0879 ,  G06F12/0897 ,  H04L69/12

摘要： Write-combining in a computer system that uses a push model is set forth herein. In one embodiment, the method comprises creating one or more packets having a descriptor and the data associated with detected write transactions stored in the buffer assigned to a write-combinable range in response to a flush request to flush the buffer, and sending (pushing) these packets to the network I/O device.

摘要翻译： 本文介绍了使用推送模型的计算机系统中的写入组合。 在一个实施例中，该方法包括：响应于冲洗缓冲器的刷新请求，创建一个或多个具有描述符的数据包，以及存储在缓冲区中的检测到的写入事务的数据，该数据被分配给可写入可组合范围，并发送（推送） 这些数据包到网络I / O设备。

公开(公告)号：US20050033874A1

公开(公告)日：2005-02-10

申请号：US10635306

申请日：2003-08-05

申请人： William Futral ,  Jie Ni

发明人： William Futral ,  Jie Ni

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： Machine-readable media, methods, and apparatus are described for transferring data. In some embodiments, an operating system may allocate pages to a buffer and may build a memory descriptor list that references the pages allocated to the buffer. A direct memory access (DMA) controller may process the memory descriptor list and transfer data between a buffer defined by the memory descriptor list and another location per the memory descriptor list. The DMA controller may further support data transfers that involve buffers defined by scatter gather lists and/or chained DMA descriptors built by a device driver.

摘要翻译： 描述了用于传送数据的机器可读介质，方法和装置。 在一些实施例中，操作系统可以向缓冲器分配页面，并且可以构建引用分配给缓冲器的页面的存储器描述符列表。 直接存储器访问（DMA）控制器可以处理存储器描述符列表，并且在由存储器描述符列表定义的缓冲器和每个存储器描述符列表的另一位置之间传送数据。 DMA控制器还可以支持涉及由设备驱动程序构建的分散收集列表和/或链接的DMA描述符定义的缓冲器的数据传输。