ROUTING PACKETS IN ON-CHIP NETWORKS
    4.
    发明申请
    ROUTING PACKETS IN ON-CHIP NETWORKS 有权
    路由网络中的路由包

    公开(公告)号:US20110161626A1

    公开(公告)日:2011-06-30

    申请号:US12648124

    申请日:2009-12-28

    IPC分类号: G06F15/76 G06F9/02

    CPC分类号: H04L47/823 G06F15/7825

    摘要: Techniques for packet routing in an on-chip network are provided. In one embodiment, a method for routing packets in a multi-core processor including multiple cores connected by an on-chip network includes identifying ports that are incorrect while routing the packet. After receiving the packet at an input port, some of the ports are excluded from consideration while selecting the output port for the packet. The output port is selected from the remaining ports and the packet is routed to the selected output port.

    摘要翻译: 提供了片上网络中分组路由的技术。 在一个实施例中,用于在包括由片上网络连接的多个核心的多核处理器中路由分组的方法包括识别在路由分组时不正确的端口。 在输入端口接收到数据包后,在选择数据包的输出端口的同时,部分端口被排除在考虑之外。 从其余端口中选择输出端口,并将数据包路由到所选输出端口。

    Programmable hardware for deep packet filtering
    9.
    发明授权
    Programmable hardware for deep packet filtering 有权
    用于深度包过滤的可编程硬件

    公开(公告)号:US07519995B2

    公开(公告)日:2009-04-14

    申请号:US11587292

    申请日:2005-04-19

    IPC分类号: G06F11/30

    摘要: An improved deep packet filter system designed to optimize search of dynamic patterns for a high speed network traffic. The improved deep packet filter system is a hardware-based system with optimized logic area. One optimization technique is the sharing of common sub-logic in the hardware design to reduce the number of gates that are required. Another optimization technique is the use of a built-in memory to store portions of the pattern set, also resulting in a reduction of gates. The reduction of the logic area allows the deep packet filter system to be implemented onto a single field-programmable array chip.

    摘要翻译: 一种改进的深度包过滤系统,旨在优化高速网络流量的动态模式搜索。 改进的深度包过滤系统是一种基于硬件的系统,具有优化的逻辑区域。 一种优化技术是在硬件设计中共享公共子逻辑,以减少所需门数。 另一个优化技术是使用内置存储器来存储图案集的部分,也导致门的减少。 逻辑区域的减少允许将深度分组过滤器系统实现到单个现场可编程阵列芯片上。

    Method of equalizing loads on a computer bus
    10.
    发明授权
    Method of equalizing loads on a computer bus 失效
    在计算机总线上均衡负载的方法

    公开(公告)号:US5793991A

    公开(公告)日:1998-08-11

    申请号:US474811

    申请日:1995-06-07

    IPC分类号: G06F13/16 G06F13/00

    CPC分类号: G06F13/1684 Y02B60/1228

    摘要: A method for translating information of balancing loads among bus segments to provide a load balanced bus system. The method includes the steps of displacing bus connection balancing loads from a least significant bit location of a digital device bus by an offset factor and translating information between the balancing load and a the digital device bus within a switch by circularly shifting the information by a number of bits equivalent to the offset factor.

    摘要翻译: 一种在总线段之间平衡负载信息的方法,以提供负载平衡总线系统。 该方法包括以下步骤:从数字设备总线的最低有效位置移位总线连接平衡负载偏移因子,并通过将信息循环移位一个数字来在交换机内的平衡负载和数字设备总线之间平移信息 的位相当于偏移因子。