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公开(公告)号：US20090027364A1
公开(公告)日：2009-01-29
申请号：US12011606
申请日：2008-01-28
CPC分类号： G09G3/20 , G09G3/2022 , G09G5/395 , G09G2310/0235 , G09G2310/0267 , G09G2310/0272
摘要： A novel method for driving a display having an array of pixels arranged in a plurality of columns and a plurality of rows includes the steps of defining a modulation period for a row of pixels, dividing the modulation period into a number of coequal time intervals equal to n times the number of rows in the array, receiving a multi-bit data word that indicates an intensity value, and updating the signal asserted on the pixel during a plurality of the time intervals such that the intensity value is displayed by the pixel. Note that n is an integer greater than zero. The method can be applied to all rows, which can be driven asynchronously. A display driver for performing the novel methods is also disclosed. The present invention facilitates driving the display at 100% bandwidth efficiency during each time interval in the modulation period.
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公开(公告)号：US06914650B2
公开(公告)日：2005-07-05
申请号：US09935403
申请日：2001-08-22
申请人： William K. Zuravleff
发明人： William K. Zuravleff
IPC分类号： G02F1/1335 , G02F1/1343 , G02F1/1368
CPC分类号： G02F1/133553 , G02F1/134336
摘要： A reflective LCD array (10) configured to minimize distortion in mirrors (14) thereof produced by attachment of a plurality of vias (16) to the mirrors (14). The vias (16) electrically connect the mirrors (14) to a metal layer (12) having circuitry thereon associated with the mirrors (14). The vias (16) are positioned equidistant about a center (30) of the mirrors (14) such that spacing of the vias (16) is generally equidistant from an X axis (26) and Y axis (28) of the reflective LCD array 10. The vias (16) are positioned such that such symmetry is retained even where circuitry associated with adjacent mirrors (14) is a reflected image copy of the reference mirror (14). Where even spacing about either the X axis (26) or the Y axis (28) is not practical, the vias (16) are grouped near the center (30) of the mirror (14) along that axis such that the effect is that of there being only a single via (16) along such axis.
摘要翻译： 一种反射型LCD阵列（10），其构造成使得通过将多个通孔（16）附接到反射镜（14）而产生的反射镜（14）中的失真最小化。 通孔（16）将反射镜（14）电连接到其上具有与反射镜（14）相关联的电路的金属层（12）。 通孔（16）围绕反射镜（14）的中心（30）等距定位，使得通孔（16）的间隔与反射型LCD阵列的X轴（26）和Y轴（28）大致等距离 10。 通孔（16）被定位成即使在与相邻反射镜（14）相关联的电路是参考反射镜（14）的反射图像副本的情况下也保持这样的对称性。 在X轴（26）或Y轴（28）周围的均匀间距不实际的情况下，通孔（16）沿着该轴线分组在反射镜（14）的中心（30）附近，使得效果是 沿这个轴线只有一个通孔（16）。
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3.发明授权Display device and driving method based on the number of pixel rows in the display 有权基于显示器中的像素行的数量的显示装置和驱动方法公开(公告)号：US08223179B2
公开(公告)日：2012-07-17
申请号：US11881732
申请日：2007-07-27
IPC分类号： G09G5/02
CPC分类号： G09G3/20 , G09G3/2022 , G09G5/395 , G09G2310/0235 , G09G2310/0267 , G09G2310/0272
摘要： A novel method for driving a display having an array of pixels arranged in a plurality of columns and a plurality of rows includes the steps of defining a modulation period for a row of pixels, dividing the modulation period into a number of coequal time intervals equal to n times the number of rows in the array, receiving a multi-bit data word that indicates an intensity value, and updating the signal asserted on the pixel during a plurality of the time intervals such that the intensity value is displayed by the pixel. Note that n is an integer greater than zero. The method can be applied to all rows, which can be driven asynchronously. A display driver for performing the novel methods is also disclosed. The present invention facilitates driving the display at 100% bandwidth efficiency during each time interval in the modulation period.
摘要翻译： 用于驱动具有排列在多列和多行中的像素阵列的显示器的新颖方法包括以下步骤：为一行像素定义调制周期，将调制周期划分为等于 n次阵列中的行数，接收指示强度值的多位数据字，并且在多个时间间隔期间更新在像素上断言的信号，使得强度值由像素显示。 请注意，n是大于零的整数。 该方法可以应用于可以异步驱动的所有行。 还公开了用于执行新颖方法的显示驱动器。 本发明便于在调制周期的每个时间间隔内以100％的带宽效率驱动显示。
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公开(公告)号：US20090027360A1
公开(公告)日：2009-01-29
申请号：US11881732
申请日：2007-07-27
IPC分类号： G06F3/038
CPC分类号： G09G3/20 , G09G3/2022 , G09G5/395 , G09G2310/0235 , G09G2310/0267 , G09G2310/0272
摘要： A novel method for driving a display having an array of pixels arranged in a plurality of columns and a plurality of rows includes the steps of defining a modulation period for a row of pixels, dividing the modulation period into a number of coequal time intervals equal to n times the number of rows in the array, receiving a multi-bit data word that indicates an intensity value, and updating the signal asserted on the pixel during a plurality of the time intervals such that the intensity value is displayed by the pixel. Note that n is an integer greater than zero. The method can be applied to all rows, which can be driven asynchronously. A display driver for performing the novel methods is also disclosed. The present invention facilitates driving the display at 100% bandwidth efficiency during each time interval in the modulation period.
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公开(公告)号：US06781566B2
公开(公告)日：2004-08-24
申请号：US09935535
申请日：2001-08-22
申请人： William K. Zuravleff
发明人： William K. Zuravleff
IPC分类号： G09G336
CPC分类号： G02F1/133553
摘要： A reflective LCD array (10) having a plurality of mirrors (40) in a mirror layer (14) of material layers (12). Underlying the mirror layer (12) are at least a second metal layer (18) and a third metal layer (20). The second metal layer (18) and the third metal layer (20) will each have a first plurality of power traces (50) and (51), arrayed such that the power traces (50) and (51) generally completely underlie a plurality of gaps (44, 46) between the mirrors (40). The power traces (50) are positioned such that the average voltage presented thereby is ½(V0+V1). This will generally prevent the buildup of a residual DC bias between the mirrors (40) and an ITO layer (32) which might otherwise cause the production of ions (38) which could degrade the performance of and perhaps damage the reflective LCD array (10).
摘要翻译： 一种具有在材料层（12）的镜层（14）中的多个反射镜（40）的反射型LCD阵列（10）。 镜面层（12）的下面至少是第二金属层（18）和第三金属层（20）。 第二金属层（18）和第三金属层（20）将各自具有第一多个功率迹线（50）和（51），排列成使得功率迹线（50）和（51）通常完全位于多个 的反射镜（40）之间的间隙（44,46）。 功率迹线（50）被定位成使得由此呈现的平均电压为½（V0 + V1）。 这通常将防止反射镜（40）和ITO层（32）之间的残余DC偏压的累积，否则可能导致产生离子（38）的ITO层（38），这可能降低反射性LCD阵列（10）的性能并可能损坏 ）。
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6.发明授权Display device and driving method using multiple pixel control units to drive respective sets of pixel rows in the display device 有权使用多个像素控制单元来驱动显示装置中的各组像素行的显示装置和驱动方法公开(公告)号：US08228356B2
公开(公告)日：2012-07-24
申请号：US12011605
申请日：2008-01-28
IPC分类号： G09G5/02
CPC分类号： G09G3/20 , G09G3/2022 , G09G5/395 , G09G2310/0235 , G09G2310/0267 , G09G2310/0272
摘要： A novel method for driving a display having an array of pixels arranged in a plurality of columns and a plurality of rows includes the steps of defining a modulation period for a row of pixels, dividing the modulation period into a number of coequal time intervals equal to n times the number of rows in the array, receiving a multi-bit data word that indicates an intensity value, and updating the signal asserted on the pixel during a plurality of the time intervals such that the intensity value is displayed by the pixel. Note that n is an integer greater than zero. The method can be applied to all rows, which can be driven asynchronously. A display driver for performing the novel methods is also disclosed. The present invention facilitates driving the display at 100% bandwidth efficiency during each time interval in the modulation period.
摘要翻译： 用于驱动具有排列在多列和多行中的像素阵列的显示器的新颖方法包括以下步骤：为一行像素定义调制周期，将调制周期划分为等于 n次阵列中的行数，接收指示强度值的多位数据字，并且在多个时间间隔期间更新在像素上断言的信号，使得强度值由像素显示。 请注意，n是大于零的整数。 该方法可以应用于可以异步驱动的所有行。 还公开了用于执行新颖方法的显示驱动器。 本发明便于在调制周期的每个时间间隔内以100％的带宽效率驱动显示。
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7.发明申请公开(公告)号：US20090027363A1
公开(公告)日：2009-01-29
申请号：US12011605
申请日：2008-01-28
IPC分类号： G06F3/038
CPC分类号： G09G3/20 , G09G3/2022 , G09G5/395 , G09G2310/0235 , G09G2310/0267 , G09G2310/0272
摘要： A novel method for driving a display having an array of pixels arranged in a plurality of columns and a plurality of rows includes the steps of defining a modulation period for a row of pixels, dividing the modulation period into a number of coequal time intervals equal to n times the number of rows in the array, receiving a multi-bit data word that indicates an intensity value, and updating the signal asserted on the pixel during a plurality of the time intervals such that the intensity value is displayed by the pixel. Note that n is an integer greater than zero. The method can be applied to all rows, which can be driven asynchronously. A display driver for performing the novel methods is also disclosed. The present invention facilitates driving the display at 100% bandwidth efficiency during each time interval in the modulation period.
摘要翻译： 用于驱动具有排列在多列和多行中的像素阵列的显示器的新颖方法包括以下步骤：为一行像素定义调制周期，将调制周期划分为等于 n次阵列中的行数，接收指示强度值的多位数据字，并且在多个时间间隔期间更新在像素上断言的信号，使得强度值由像素显示。 请注意，n是大于零的整数。 该方法可以应用于可以异步驱动的所有行。 还公开了用于执行新颖方法的显示驱动器。 本发明便于在调制周期的每个时间间隔内以100％的带宽效率驱动显示。
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公开(公告)号：US20090027361A1
公开(公告)日：2009-01-29
申请号：US12011520
申请日：2008-01-28
CPC分类号： G09G3/20 , G09G3/2022 , G09G5/395 , G09G2310/0235 , G09G2310/0267 , G09G2310/0272
摘要： A novel method for driving a display having an array of pixels arranged in a plurality of columns and a plurality of rows includes the steps of defining a modulation period for a row of pixels, dividing the modulation period into a number of coequal time intervals equal to n times the number of rows in the array, receiving a multi-bit data word that indicates an intensity value, and updating the signal asserted on the pixel during a plurality of the time intervals such that the intensity value is displayed by the pixel. Note that n is an integer greater than zero. The method can be applied to all rows, which can be driven asynchronously. A display driver for performing the novel methods is also disclosed. The present invention facilitates driving the display at 100% bandwidth efficiency during each time interval in the modulation period.
摘要翻译： 用于驱动具有排列在多列和多行中的像素阵列的显示器的新颖方法包括以下步骤：为一行像素定义调制周期，将调制周期划分为等于 n次阵列中的行数，接收指示强度值的多位数据字，并且在多个时间间隔期间更新在像素上断言的信号，使得强度值由像素显示。 请注意，n是大于零的整数。 该方法可以应用于可以异步驱动的所有行。 还公开了用于执行新颖方法的显示驱动器。 本发明便于在调制周期的每个时间间隔内以100％的带宽效率驱动显示。
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公开(公告)号：US06731404B1
公开(公告)日：2004-05-04
申请号：US09433114
申请日：1999-11-03
申请人： William K. Zuravleff
发明人： William K. Zuravleff
IPC分类号： G06K1500
CPC分类号： H04N1/4052 , H04N1/4055
摘要： Circuits for rendering according to the present invention are operable to function in either halftone mode or error diffusion mode. A pixel multiplexor selects between a rasterized unrendered pixel signal from an input rasterized unrendered datastream in halftone mode and an error diffusion adjusted pixel signal generated by error diffusion hardware in error diffusion mode. A memory stores the current error diffusion state signal and retrieves it as the previous error diffusion state signal during the processing of the appropriate pixel in the next scan line in error diffusion mode. A threshold multiplexor selects between an error diffusion threshold signal and a halftone threshold signal. In halftone mode, the memory is operable to retrieve a halftone threshold signal which is supplied to the threshold multiplexor. A read address generator provides a read address signal to the memory for indicating the memory location from which to read either the previous error diffusion state signal or the halftone threshold signal. The read address generator includes a read address multiplexor for selecting between an error diffusion read address signal and a halftone read address signal. The read address generator further includes a stride multiplexor for providing the selected stride signal. The stride multiplexor has at least two stride inputs which receive stride signals corresponding to the appropriate stride values for error diffusion mode and halftone mode. A reset multiplexor provides the capability to set the read address signal either to a predetermined starting read address signal value or to the next read address signal.
摘要翻译： 根据本发明的用于渲染的电路可操作以在半色调模式或误差扩散模式下起作用。 像素多路复用器在半色调模式的输入光栅化未渲染数据流的光栅化未渲染像素信号和误差扩散模式中由误差扩散硬件产生的误差扩散调整像素信号之间进行选择。 存储器存储当前误差扩散状态信号，并且在误差扩散模式中在下一个扫描行中的适当像素的处理期间将其作为先前的误差扩散状态信号进行检索。 阈值多路复用器在误差扩散阈值信号和半色调阈值信号之间进行选择。 在半色调模式下，存储器可操作以检索提供给阈值多路复用器的半色调阈值信号。 读地址生成器向存储器提供读地址信号，用于指示从其读取先前错误扩散状态信号或半色调阈值信号的存储器位置。 读地址生成器包括用于在误差扩散读地址信号和半色调读地址信号之间进行选择的读地址多路复用器。 读取地址生成器还包括用于提供所选步幅信号的步幅多路复用器。 步进多路复用器具有至少两个步进输入，其接收对应于用于误差扩散模式和半色调模式的适当步幅值的步幅信号。 复位复用器提供将读取地址信号设置为预定的开始读取地址信号值或下一个读取地址信号的能力。
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10.发明授权System for placing entries of an outstanding processor request into a free pool after the request is accepted by a corresponding peripheral device 失效在请求被相应的外围设备接受之后，将未完成的处理器请求的条目放入空闲池中的系统
公开(公告)号：US5737547A
公开(公告)日：1998-04-07
申请号：US480739
申请日：1995-06-07
CPC分类号： G06F9/3824
摘要： A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.
摘要翻译： 提供非阻塞负载缓冲器用于高速微处理器和存储器系统。 非阻塞负载缓冲器将高速处理器/高速缓存总线接口，该总线将处理器和高速缓存连接到非阻塞负载缓冲区，其中低速外设总线连接到外围设备。 非阻塞负载缓冲器允许以相对较低带宽的外围设备从外围设备的最大速率直接从处理器的编程I / O检索数据，从而可以处理和存储数据，而不会使处理器无需空闲。 可以同时缓冲多处理器内的多个处理器的I / O请求，以便可以在设备的等待时间期间处理多个非阻塞负载。 因此，通过处理器的编程I / O实现来自多个I / O设备的连续最大吞吐量，并且可以减少完成任务和处理数据所需的时间。 此外，提供了多重优先级的非阻塞负载缓冲器，用于通过基于优先级的存储器和外设访问调度来服务运行不同期限的实时处理的多处理器。
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