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    System for placing entries of an outstanding processor request into a free pool after the request is accepted by a corresponding peripheral device
    1.
    发明授权
    System for placing entries of an outstanding processor request into a free pool after the request is accepted by a corresponding peripheral device 失效
    在请求被相应的外围设备接受之后，将未完成的处理器请求的条目放入空闲池中的系统

    公开(公告)号：US5737547A

    公开(公告)日：1998-04-07

    申请号：US480739

    申请日：1995-06-07

    申请人： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

    发明人： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

    IPC分类号： G06F9/38 ,  G06F13/36 ,  G06F9/22

    CPC分类号： G06F9/3824

    摘要： A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

    摘要翻译： 提供非阻塞负载缓冲器用于高速微处理器和存储器系统。 非阻塞负载缓冲器将高速处理器/高速缓存总线接口，该总线将处理器和高速缓存连接到非阻塞负载缓冲区，其中低速外设总线连接到外围设备。 非阻塞负载缓冲器允许以相对较低带宽的外围设备从外围设备的最大速率直接从处理器的编程I / O检索数据，从而可以处理和存储数据，而不会使处理器无需空闲。 可以同时缓冲多处理器内的多个处理器的I / O请求，以便可以在设备的等待时间期间处理多个非阻塞负载。 因此，通过处理器的编程I / O实现来自多个I / O设备的连续最大吞吐量，并且可以减少完成任务和处理数据所需的时间。 此外，提供了多重优先级的非阻塞负载缓冲器，用于通过基于优先级的存储器和外设访问调度来服务运行不同期限的实时处理的多处理器。

    Method for storing prioritized memory or I/O transactions in queues having one priority level less without changing the priority when space available in the corresponding queues exceed
    2.
    发明授权
    Method for storing prioritized memory or I/O transactions in queues having one priority level less without changing the priority when space available in the corresponding queues exceed 失效
    在具有一个优先级的队列中存储优先级存储器或I / O事务的方法，而不改变相应队列中可用空间的优先级超过

    公开(公告)号：US5867735A

    公开(公告)日：1999-02-02

    申请号：US20859

    申请日：1998-02-09

    申请人： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

    发明人： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

    IPC分类号： G06F9/38 ,  G06F15/00 ,  G06F15/20

    CPC分类号： G06F9/3824

    摘要： A non-blocking load buffer is provided for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

    摘要翻译： 提供非阻塞负载缓冲器用于高速微处理器和存储器系统。 非阻塞负载缓冲器将高速处理器/高速缓存总线接口，该总线将处理器和高速缓存连接到非阻塞负载缓冲区，其中低速外设总线连接到外围设备。 非阻塞负载缓冲器允许以相对较低带宽的外围设备从外围设备的最大速率直接从处理器的编程I / O检索数据，从而可以处理和存储数据，而不会使处理器无需空闲。 可以同时缓冲多处理器内的多个处理器的I / O请求，以便可以在设备的等待时间期间处理多个非阻塞负载。 因此，通过处理器的编程I / O实现来自多个I / O设备的连续最大吞吐量，并且可以减少完成任务和处理数据所需的时间。 此外，提供了多重优先级的非阻塞负载缓冲器，用于通过基于优先级的存储器和外设访问调度来服务运行不同期限的实时处理的多处理器。

    Non-blocking load buffer and a multiple-priority memory system for real-time multiprocessing
    3.
    发明授权
    Non-blocking load buffer and a multiple-priority memory system for real-time multiprocessing 失效
    非阻塞负载缓冲区和用于实时多处理的多优先级存储系统

    公开(公告)号：US5812799A

    公开(公告)日：1998-09-22

    申请号：US480738

    申请日：1995-06-07

    申请人： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

    发明人： William K. Zuravleff ,  Mark Semmelmeyer ,  Timothy Robinson ,  Scott Furman

    IPC分类号： G06F13/42 ,  H01J13/00

    CPC分类号： G06F13/4243

    摘要： A non-blocking load buffer for use in a high-speed microprocessor and memory system. The non-blocking load buffer interfaces a high-speed processor/cache bus, which connects a processor and a cache to the non-blocking load buffer, with a lower speed peripheral bus, which connects to peripheral devices. The non-blocking load buffer allows data to be retrieved from relatively low bandwidth peripheral devices directly from programmed I/O of the processor at the maximum rate of the peripherals so that the data may be processed and stored without unnecessarily idling the processor. I/O requests from several processors within a multiprocessor may simultaneously be buffered so that a plurality of non-blocking loads may be processed during the latency period of the device. As a result, a continuous maximum throughput from multiple I/O devices by the programmed I/O of the processor is achieved and the time required for completing tasks and processing data may be reduced. Also, a multiple priority non-blocking load buffer is provided for serving a multiprocessor running real-time processes of varying deadlines by prioritization-based scheduling of memory and peripheral accesses.

    摘要翻译： 用于高速微处理器和存储器系统的非阻塞负载缓冲器。 非阻塞负载缓冲器将高速处理器/高速缓存总线接口，该总线将处理器和高速缓存连接到非阻塞负载缓冲区，其中低速外设总线连接到外围设备。 非阻塞负载缓冲器允许以相对较低带宽的外围设备从外围设备的最大速率直接从处理器的编程I / O检索数据，从而可以处理和存储数据，而不会使处理器无需空闲。 可以同时缓冲多处理器内的多个处理器的I / O请求，以便可以在设备的等待时间期间处理多个非阻塞负载。 因此，通过处理器的编程I / O实现来自多个I / O设备的连续最大吞吐量，并且可以减少完成任务和处理数据所需的时间。 此外，提供了多重优先级的非阻塞负载缓冲器，用于通过基于优先级的存储器和外设访问调度来服务运行不同期限的实时处理的多处理器。

    Processor system with dual clock
    4.
    发明授权
    Processor system with dual clock 失效
    处理器系统具有双时钟

    公开(公告)号：US5381543A

    公开(公告)日：1995-01-10

    申请号：US206563

    申请日：1994-03-03

    申请人： James S. Blomgren ,  Mark Semmelmeyer ,  Tuan Luong ,  Gary Baum

    发明人： James S. Blomgren ,  Mark Semmelmeyer ,  Tuan Luong ,  Gary Baum

    IPC分类号： G06F13/42 ,  G06F1/06

    CPC分类号： G06F13/4217

    摘要： The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e. the address status signal) generated by the CPU. The ADS and RDY signals must be modified in a first way if the CPU calls for a memory cycle at the beginning of a bus cycle and in a second way if the CPU calls for a memory cycle in the middle of a CPU cycle. The use of a CPU clock speed doubler in combination with a write-back cache achieves truly synergistic increases in system speed.

    摘要翻译： 本发明提供了一种用于在存储器总线的周期速度的多频道处在单个微处理器中操作CPU的装置。 利用本发明，提供了第一和第二定时信号。 第二定时信号的频率是第一定时信号的频率的倍数。 将第二或快速定时信号提供给CPU，并将第一或更慢的定时信号提供给存储器子系统。 总线接口单元插在CPU和存储器总线之间。 该总线接口单元从存储器子系统接收RDY信号（即就绪信号），并在将其提供给CPU之前对其进行修改。 来自存储器子系统的“就绪”信号在每个总线周期的很大部分处于未定义状态。 由于在每个存储器访问期间至少发生两个CPU周期，因此总线接口单元必须确保CPU不会误解来自存储器子系统的就绪信号。 总线接口单元还必须修改由CPU产生的ADS信号（即地址状态信号）。 如果CPU在总线周期开始时要求存储器周期，并且如果CPU在CPU周期中要求存储器周期，则ADS和RDY信号必须以第一种方式进行修改。 使用CPU时钟速度倍增器与回写缓存相结合，实现了系统速度的真正协同增长。

    Computer system architecture implementing split instruction and operand cache line-pair-state management
    5.
    发明授权
    Computer system architecture implementing split instruction and operand cache line-pair-state management 失效
    计算机系统架构实现分割指令和操作数高速缓存线对状态管理

    公开(公告)号：US5095424A

    公开(公告)日：1992-03-10

    申请号：US384867

    申请日：1989-07-21

    申请人： Gary A. Woffinden ,  Theodore S. Robinson ,  Jeffrey A. Thomas ,  Robert A. Ertl ,  James P. Millar ,  Christopher D. Finan ,  Joseph A. Petolino ,  Ajay Shah ,  Shen H. Wang ,  Mark Semmelmeyer

    发明人： Gary A. Woffinden ,  Theodore S. Robinson ,  Jeffrey A. Thomas ,  Robert A. Ertl ,  James P. Millar ,  Christopher D. Finan ,  Joseph A. Petolino ,  Ajay Shah ,  Shen H. Wang ,  Mark Semmelmeyer

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0848

    摘要： A computer system architecture implementing multiple central processing units, each including a split instruction and operand cache, and that provides for the management of multiple copies (line pairs) of a memory line through the use of a line pair state is described. Systematic management of memory lines when transferred with respect to instruction and operand data cache memories allows the integrity of the system to be maintained at all times. The split cache architecture management determines whether a memory line having a first predetermined system address is present within both the instruction and operand cache memories or will be upon move-in of a memory line. Address tag line pair state information is maintained to allow determinations of whether and where the respective memory line pair members reside. The architecture implements the management of the line pairs on each transfer of a memory line to any of the split caches of the system. A line pair is allowed to exist whenever the same memory line exists in the same relative location in each of the instruction and operand cache buffers of a single central processor. The architecture further includes a data path selector for transferring operand data to either the instruction or operand data cache buffers, or both, depending on whether the operand buffer destination is a memory line that is a member of a line pair.

    摘要翻译： 描述了实现多个中央处理单元的计算机系统架构，每个中央处理单元包括分割指令和操作数高速缓存，并且通过使用线对状态来管理存储器线的多个副本（线对）。 当对指令和操作数数据高速缓存存储器进行传输时，对存储器线路的系统管理允许始终保持系统的完整性。 分割高速缓存架构管理确定在指令和操作数高速缓存存储器内是否存在具有第一预定系统地址的存储器线，或者将在存储器线路中移入。 维持地址标签线对状态信息以允许确定各个存储器线对成员是否存在和在何处驻留。 该架构在将存储器线路的每次传送到系统的任何分割高速缓存时实现线对的管理。 只要在单个中央处理器的每个指令和操作数缓存缓冲器中的相同相对位置存在相同的存储器线，就允许线对存在。 该架构还包括数据路径选择器，用于根据操作数缓冲目标是作为线对的成员的存储线，将操作数数据传送到指令或操作数数据高速缓冲存储器或两者。

    Processor system with dual clock
    6.
    发明授权
    Processor system with dual clock 失效
    处理器系统具有双时钟

    公开(公告)号：US5325516A

    公开(公告)日：1994-06-28

    申请号：US848544

    申请日：1992-03-09

    申请人： James S. Blomgren ,  Mark Semmelmeyer ,  Tuan Luong ,  Gary Baum

    发明人： James S. Blomgren ,  Mark Semmelmeyer ,  Tuan Luong ,  Gary Baum

    IPC分类号： G06F13/42 ,  G06F13/00

    CPC分类号： G06F13/4217

    摘要： The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing signal is a multiple of the frequency of the first timing signal. The second or fast timing signal is provided to the CPU and the first or slower timing signal is provided to the memory subsystem. A bus interface unit is interposed between the CPU and the memory bus. This bus interface unit receives the RDY signal (i.e. the ready signal) from the memory subsystem and modifies it before it is provided to the CPU. The "ready" signal from the memory subsystem is in an undefined state for a significant portion of each bus cycle. Since at least two CPU cycles occur during each memory access, the bus interface unit must ensure that the CPU does not misinterpret the ready signal from the memory subsystem. The bus interface unit also must modify the ADS signal (i.e. the address status signal) generated by the CPU. The ADS and RDY signals must be modified in a first way if the CPU calls for a memory cycle at the beginning of a bus cycle and in a second way if the CPU calls for a memory cycle in the middle of a CPU cycle. The use of a CPU clock speed doubler in combination with a write-back cache achieves truly synergistic increases in system speed.

    摘要翻译： 本发明提供了一种用于在存储器总线的周期速度的多频道处在单个微处理器中操作CPU的装置。 利用本发明，提供了第一和第二定时信号。 第二定时信号的频率是第一定时信号的频率的倍数。 将第二或快速定时信号提供给CPU，并将第一或更慢的定时信号提供给存储器子系统。 总线接口单元插在CPU和存储器总线之间。 该总线接口单元从存储器子系统接收RDY信号（即就绪信号），并在将其提供给CPU之前对其进行修改。 来自存储器子系统的“就绪”信号在每个总线周期的很大部分处于未定义状态。 由于在每个存储器访问期间至少发生两个CPU周期，因此总线接口单元必须确保CPU不会误解来自存储器子系统的就绪信号。 总线接口单元还必须修改由CPU产生的ADS信号（即地址状态信号）。 如果CPU在总线周期开始时要求存储器周期，并且如果CPU在CPU周期中要求存储器周期，则ADS和RDY信号必须以第一种方式进行修改。 使用CPU时钟速度倍增器与回写缓存相结合，实现了系统速度的真正协同增长。