公开(公告)号：US6128692A

公开(公告)日：2000-10-03

申请号：US96251

申请日：1998-06-11

申请人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff ,  L. Todd Cope ,  William Leong, deceased ,  by Louis Leong, legal representative

发明人： Chiakang Sung ,  Wanli Chang ,  Joseph Huang ,  Richard G. Cliff ,  L. Todd Cope ,  William Leong, deceased ,  by Louis Leong, legal representative

IPC分类号： G11C8/04 ,  G11C8/12 ,  H03K19/177 ,  G06F12/02

CPC分类号： G11C8/04 ,  G11C8/12 ,  H03K19/17704 ,  H03K19/1776 ,  H03K19/17764

摘要： A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circuitry associated with the large block, and especially the circuitry for addressing that block during programming and/or verification of the device, the address decoder that is normally used to address the block during use of the device to perform logic is also used during programming and/or verification. During programming and/or verification a counter or other similar coded address signal generating circuitry is used to supply address information to the decoder.

摘要翻译： 可编程逻辑阵列集成电路器件除了通常的可编程逻辑模块和通常的可编程互连导体网络之外，还具有相对较大的可编程存储单元块。 为了简化与大块相关联的电路，特别是用于在设备的编程和/或验证期间寻址该块的电路，在使用设备执行逻辑期间通常用于寻址块的地址解码器是 也在编程和/或验证期间使用。 在编程和/或验证期间，使用计数器或其它类似的编码地址信号产生电路来向解码器提供地址信息。