Preparing instruction groups for a processor having multiple issue ports
    1.
    发明授权
    Preparing instruction groups for a processor having multiple issue ports 有权
    为具有多个发行端口的处理器准备指令组

    公开(公告)号:US07934203B2

    公开(公告)日:2011-04-26

    申请号:US11139232

    申请日:2005-05-27

    IPC分类号: G06F9/45 G06F9/30

    CPC分类号: G06F9/45516 G06F9/3885

    摘要: During program code conversion, such as in a dynamic binary translator, automatic code generation provides target code 21 executable by a target processor 13. Multiple instruction ports 610 disperse a group of instructions to functional units 620 of the processor 13. Disclosed is a mechanism of preparing an instruction group 606 using a plurality of pools 700 having a hierarchical structure 711-715. Each pool represents a different overlapping subset of the issue ports 610. Placing an instruction 600 into a particular pool 700 also reduces vacancies in any one or more subsidiary pools in the hierarchy. In a preferred embodiment, a counter value 702 is associated with each pool 700 to track vacancies. A valid instruction group 606 is formed by picking the placed instructions 600 from the pools 700. The instruction groups are generated accurately and automatically. Decoding errors and stalls are minimized or completely avoided.

    摘要翻译: 在程序代码转换期间,例如在动态二进制转换器中,自动代码生成提供可由目标处理器13执行的目标代码21.多个指令端口610将一组指令分散到处理器13的功能单元620中。公开了一种机制 使用具有分层结构711-715的多个池700准备指令组606。 每个池代表问题端口610的不同重叠子集。将指令600放置到特定池700中还可以降低层级中任何一个或多个子池中的空位。 在优选实施例中,计数器值702与每个池700相关联以跟踪空位。 通过从池700拾取所放置的指令600来形成有效指令组606.准确且自动地生成指令组。 解码错误和失速被最小化或完全避免。

    RETURN ADDRESS OPTIMISATION FOR A DYNAMIC CODE TRANSLATOR

    公开(公告)号:US20130024675A1

    公开(公告)日:2013-01-24

    申请号:US13479026

    申请日:2012-05-23

    IPC分类号: G06F9/38

    摘要: A dynamic code translator with isoblocking uses a return trampoline having branch instructions conditioned on different isostates to optimize return address translation, by allowing the hardware to predict that the address of a future return will be the address of trampoline. An IP relative call is inserted into translated code to write the trampoline address to a target link register and a target return address stack used by the native machine to predict return addresses. If a computed subject return address matches a subject return address register value, the current isostate of the isoblock is written to an isostate register. The isostate value in the isostate register is then used to select the branch instruction in the trampoline for the true subject return address. Sufficient code area in the trampoline instruction set can be reserved for a number of compare/branch pairs which is equal to the number of available isostates.

    RETURN ADDRESS OPTIMISATION FOR A DYNAMIC CODE TRANSLATOR
    3.
    发明申请
    RETURN ADDRESS OPTIMISATION FOR A DYNAMIC CODE TRANSLATOR 审中-公开
    动态代码转换器的返回地址优化

    公开(公告)号:US20130024674A1

    公开(公告)日:2013-01-24

    申请号:US13186831

    申请日:2011-07-20

    IPC分类号: G06F9/30

    摘要: A dynamic code translator with isoblocking uses a return trampoline having branch instructions conditioned on different isostates to optimize return address translation, by allowing the hardware to predict that the address of a future return will be the address of trampoline. An IP relative call is inserted into translated code to write the trampoline address to a target link register and a target return address stack used by the native machine to predict return addresses. If a computed subject return address matches a subject return address register value, the current isostate of the isoblock is written to an isostate register. The isostate value in the isostate register is then used to select the branch instruction in the trampoline for the true subject return address. Sufficient code area in the trampoline instruction set can be reserved for a number of compare/branch pairs which is equal to the number of available isostates.

    摘要翻译: 具有等压锁定的动态代码转换器使用返回蹦床,其具有在不同等值线上调节的分支指令以优化返回地址转换,通过允许硬件预测未来回报的地址将是蹦床的地址。 将IP相关调用插入到转换的代码中,以将蹦床地址写入目标链接寄存器和由本机使用的目标返回地址堆栈来预测返回地址。 如果计算的主题返回地址与主题返回地址寄存器值相匹配,则将等压锁定的当前等值线写入等势寄存器。 等静币寄存器中的等值线值用于选择蹦床中的分支指令,以获得真实的主题返回地址。 蹦床指令集中的足够的代码区域可以为等于可用等值体数的多个比较/分支对保留。

    Return address optimisation for a dynamic code translator
    4.
    发明授权
    Return address optimisation for a dynamic code translator 有权
    为动态代码转换器返回地址优化

    公开(公告)号:US08893100B2

    公开(公告)日:2014-11-18

    申请号:US13479026

    申请日:2012-05-23

    摘要: A dynamic code translator with isoblocking uses a return trampoline having branch instructions conditioned on different isostates to optimize return address translation, by allowing the hardware to predict that the address of a future return will be the address of trampoline. An IP relative call is inserted into translated code to write the trampoline address to a target link register and a target return address stack used by the native machine to predict return addresses. If a computed subject return address matches a subject return address register value, the current isostate of the isoblock is written to an isostate register. The isostate value in the isostate register is then used to select the branch instruction in the trampoline for the true subject return address. Sufficient code area in the trampoline instruction set can be reserved for a number of compare/branch pairs which is equal to the number of available isostates.

    摘要翻译: 具有等压锁定的动态代码转换器使用返回蹦床,其具有在不同等值线上调节的分支指令以优化返回地址转换,通过允许硬件预测未来回报的地址将是蹦床的地址。 将IP相关调用插入到转换的代码中,以将蹦床地址写入目标链接寄存器和由本机使用的目标返回地址堆栈来预测返回地址。 如果计算的主题返回地址与主题返回地址寄存器值相匹配,则将等压锁定的当前等值线写入等势寄存器。 等静币寄存器中的等值线值用于选择蹦床中的分支指令,以获得真实的主题返回地址。 蹦床指令集中的足够的代码区域可以为等于可用等值体数的多个比较/分支对保留。