公开(公告)号：US4975929A

公开(公告)日：1990-12-04

申请号：US405799

申请日：1989-09-11

申请人： William R. Apple ,  William R. Freeman ,  Paulmer M. Soderberg

发明人： William R. Apple ,  William R. Freeman ,  Paulmer M. Soderberg

IPC分类号： H04L7/033 ,  H04L7/04

CPC分类号： H04L7/0338 ,  H04L7/044

摘要： A digital phase acquisition circuit includes logic for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for a clock for recovering information representative of the data. The circuit allows clock to be recovered within 1 bit time of a predetermined data transition occurring, thus allowing preambles of 1 bit to be utilized in data packets.

摘要翻译： 数字相位获取电路包括用于检测输入数据和多个候选时钟相位的边缘的逻辑，该电路还包括用于确定数据何时经历相变的逻辑和经历数字等效转换的至少一个候选相位 时间到数据转换，以使候选阶段能够用于恢复表示数据的信息的时钟。 电路允许在发生预定数据转换的1位时间内恢复时钟，从而允许在数据分组中使用1比特的前导码。

公开(公告)号：US4959846A

公开(公告)日：1990-09-25

申请号：US405806

申请日：1989-09-11

申请人： William R. Apple ,  William R. Freeman ,  Paulmer M. Soderberg ,  Lyle Thompson ,  Mark S. Thomas

发明人： William R. Apple ,  William R. Freeman ,  Paulmer M. Soderberg ,  Lyle Thompson ,  Mark S. Thomas

IPC分类号： H04L7/033 ,  H04L7/04

CPC分类号： H04L7/0338 ,  H04L7/044

摘要： A digital phase acquisition circuit includes circuits for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a predetermined phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for choosing an appropriate clock phase for recovering information representative of the data. The circuit further includes logic for comparing a frequency of the chosen clock pulse and the data and adjusting at least one of these frequencies when a predetermined amount of drift therebetween is detected. The invention allows clock to be recovered within 1 bit time of a predetermined data transition occurring and allows an appropriate clock to be maintained through an entire packet regardless of packet length.

摘要翻译： 数字相位获取电路包括用于检测输入数据和多个候选时钟相位的边缘的电路，该电路还包括用于确定数据何时经历预定相位转移的逻辑和经历数字等效转换关闭的至少一个候选相位 在时间上进行数据转换，以便使候选阶段能够用于选择用于恢复表示数据的信息的适当的时钟相位。 电路还包括用于比较所选择的时钟脉冲和数据的频率并在检测到预定量的漂移之间时调整这些频率中的至少一个的逻辑。 本发明允许在发生预定数据转换的1位时间内恢复时钟，并允许通过整个分组维持适当的时钟，而不管分组长度如何。