公开(公告)号：US20100285645A1

公开(公告)日：2010-11-11

申请号：US12838826

申请日：2010-07-19

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US08293604B2

公开(公告)日：2012-10-23

申请号：US12838826

申请日：2010-07-19

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US07781287B2

公开(公告)日：2010-08-24

申请号：US12022329

申请日：2008-01-30

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US20080124869A1

公开(公告)日：2008-05-29

申请号：US12022329

申请日：2008-01-30

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US07348628B2

公开(公告)日：2008-03-25

申请号：US11448437

申请日：2006-06-07

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级上的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US20070012996A1

公开(公告)日：2007-01-18

申请号：US11448437

申请日：2006-06-07

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L31/00 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级上的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。