公开(公告)号：US20100285645A1

公开(公告)日：2010-11-11

申请号：US12838826

申请日：2010-07-19

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US08293604B2

公开(公告)日：2012-10-23

申请号：US12838826

申请日：2010-07-19

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US07781287B2

公开(公告)日：2010-08-24

申请号：US12022329

申请日：2008-01-30

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US20080124869A1

公开(公告)日：2008-05-29

申请号：US12022329

申请日：2008-01-30

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US07348628B2

公开(公告)日：2008-03-25

申请号：US11448437

申请日：2006-06-07

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级上的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US20070012996A1

公开(公告)日：2007-01-18

申请号：US11448437

申请日：2006-06-07

申请人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Choong-Ho Lee ,  Seong-Goo Kim ,  Won-sok Lee ,  Seung-bae Park

IPC分类号： H01L31/00 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/792 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/115 ,  H01L27/11568 ,  H01L28/91 ,  H01L29/66833 ,  H01L29/7926

摘要： Vertical channel semiconductor devices include a semiconductor substrate with a pillar having an upper surface. An insulated gate electrode is around a periphery of the pillar. The insulated gate electrode has an upper surface at a vertical level lower than the upper surface of the pillar to vertically space apart the insulated gate electrode from the upper surface of the pillar. A first source/drain region is in the substrate adjacent the pillar. A second source/drain region is disposed in an upper region of the pillar including the upper surface of the pillar. A contact pad contacts the entire upper surface of the pillar to electrically connect to the second source/drain region.

摘要翻译： 垂直沟道半导体器件包括具有上表面的柱的半导体衬底。 绝缘栅电极围绕柱的周边。 绝缘栅电极具有比柱的上表面低的垂直级上的上表面，以使绝缘栅电极与柱的上表面垂直间隔开。 第一源极/漏极区域在与衬底相邻的衬底中。 第二源极/漏极区域设置在包括柱的上表面的柱的上部区域中。 接触焊盘接触柱的整个上表面以电连接到第二源/漏区。

公开(公告)号：US07586149B2

公开(公告)日：2009-09-08

申请号：US11541756

申请日：2006-10-02

申请人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

IPC分类号： H01L23/528 ,  H01L27/108

CPC分类号： H01L29/66666 ,  H01L21/823885 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： A circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device. The circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region, bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction, channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another, gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars, and buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region.

摘要翻译： 一种包括连接到掩埋位线的垂直晶体管的电路器件和制造该电路器件的方法。 该电路装置包括半导体衬底，该半导体衬底包括外围电路区域和在外围电路区域的两侧的左侧和右侧电池区域，布置在半导体衬底上的底部有源区域在列方向上彼此间隔开并从 所述外围电路区域与所述左侧单元区域和右侧单元区域交替地排列成行方向，所述通道柱从所述底部有源区域沿垂直方向突出并且被配置为在所述行方向上彼此对准并且彼此间隔开，栅电极 设置有栅介电层并且被附接到环绕通道柱的侧表面，以及沿底部有源区延伸的掩埋位线，底部有源区包括底部源极/漏极区。

公开(公告)号：US20070075359A1

公开(公告)日：2007-04-05

申请号：US11541756

申请日：2006-10-02

申请人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

发明人： Jae-man Yoon ,  Dong-gun Park ,  Kang-yoon Lee ,  Choong-ho Lee ,  Bong-soo Kim ,  Seong-goo Kim ,  Hyeoung-won Seo ,  Seung-bae Park

IPC分类号： H01L21/8238

CPC分类号： H01L29/66666 ,  H01L21/823885 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device, the circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region; bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction; channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another; gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars; buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region; local interconnection lines contacting side surfaces of the gate electrodes in the peripheral circuit region and extending between the gate electrodes to commonly interconnect the gate electrodes in the peripheral circuit region, thereby configuring a peripheral circuit; signal lines electrically connected to upper surfaces of the channel pillars or to at least one of the local interconnection lines; and interconnection contacts electrically connecting the local interconnection line to the buried bitline of a different row from that of the commonly-connected gate electrodes or electrically connecting the local interconnection lines to the signal lines, thereby configuring the peripheral circuit.

摘要翻译： 在包括连接到掩埋位线的垂直晶体管的电路器件和制造电路器件的方法中，电路器件包括半导体衬底，该半导体衬底包括外围电路区域和外围电路区域两侧的左右单元区域; 布置在半导体衬底上的底部有源区域在列方向上彼此间隔开并且从外围电路区域交替地延伸到左小区区域和右小区区域在行方向上延伸; 通道柱从垂直方向从底部有源区域突出并且布置成在行方向上对齐并且彼此间隔开; 栅极电极设置有栅极电介质层并附接到环绕通道柱的侧表面; 掩埋位线沿着底部有源区延伸，底部有源区域包括底部源极/漏极区域; 局部互连线与外围电路区域中的栅电极的侧表面接触并在栅电极之间延伸，以在外围电路区域中共同连接栅电极，从而构成外围电路; 信号线电连接到通道柱的上表面或至少一个局部互连线; 以及互连触点将本地互连线电连接到与共用栅极电极的不同行的掩埋位线或将本地互连线电连接到信号线，从而配置外围电路。

公开(公告)号：US20110186923A1

公开(公告)日：2011-08-04

申请号：US13085898

申请日：2011-04-13

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L29/78

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

公开(公告)号：US08283714B2

公开(公告)日：2012-10-09

申请号：US13085898

申请日：2011-04-13

申请人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

发明人： Hyeoung-won Seo ,  Bong-soo Kim ,  Dong-gun Park ,  Kang-yoon Lee ,  Jae-man Yoon ,  Seong-goo Kim ,  Seung-bae Park

IPC分类号： H01L29/94

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.

摘要翻译： 两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。 在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件 。 像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。 因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，从而容易地制造高度集成的半导体存储器件。