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    APPARATUS AND METHOD FOR CYBER-ATTACK PREVENTION
    3.
    发明申请
    APPARATUS AND METHOD FOR CYBER-ATTACK PREVENTION 审中-公开
    装置和方法，用于防止病毒感染

    公开(公告)号：US20130167219A1

    公开(公告)日：2013-06-27

    申请号：US13616670

    申请日：2012-09-14

    申请人： Woo-Sug JUNG ,  Jong-Dae PARK ,  Byung-Ho YAE ,  Tae-Soo CHUNG ,  Sung-Kee NOH ,  Sung-Jin MOON ,  Nam-Seok KO ,  Hwan-Jo HEO

    发明人： Woo-Sug JUNG ,  Jong-Dae PARK ,  Byung-Ho YAE ,  Tae-Soo CHUNG ,  Sung-Kee NOH ,  Sung-Jin MOON ,  Nam-Seok KO ,  Hwan-Jo HEO

    IPC分类号： G06F21/20

    CPC分类号： H04L63/1425 ,  H04L63/1458

    摘要： Provided are a method of preventing cyber-attack based on a terminal and a terminal apparatus therefor. The terminal apparatus includes: a packet processor configured to determine whether excessive traffic is generated by a transmission packet; an anomalous traffic detecting unit configured to determine whether anomalous traffic is generated, using a first condition of the excessive traffic being maintained for a first time period and a second condition of a generation count of the same kind of transmission packets exceeding a predetermined threshold value for a second time period; and a traffic block request unit configured to generate a traffic block request signal for requesting blockage of the transmission packet according to the result of determining whether anomalous traffic is generated.

    摘要翻译： 提供一种基于终端及其终端装置来防止网络攻击的方法。 终端装置包括：分组处理器，被配置为确定是否由传输分组产生过量业务; 异常业务检测单元，被配置为使用在第一时间段内保持过多业务的第一条件和超过预定阈值的相同类型的发送分组的生成计数的第二条件来确定是否产生异常业务， 第二个时期; 以及业务块请求单元，被配置为根据确定是否产生异常业务的结果来生成用于请求阻塞所述传输分组的业务块请求信号。

    Method and apparatus for controlling direct memory access
    4.
    发明授权
    Method and apparatus for controlling direct memory access 有权
    用于控制直接存储器访问的方法和装置

    公开(公告)号：US08037214B2

    公开(公告)日：2011-10-11

    申请号：US11932718

    申请日：2007-10-31

    申请人： In Ki Hwang ,  Woo Sug Jung ,  Do Young Kim

    发明人： In Ki Hwang ,  Woo Sug Jung ,  Do Young Kim

    IPC分类号： G06F13/28 ,  H04L12/56

    CPC分类号： G06F13/32

    摘要： Provided are a method and apparatus for controlling direct memory access. In the method, data to be transmitted are read and stored in response to a direct memory access controller (DMAC) operation request, and a portion of the data corresponding to an initial burst size is first transmitted to a data destination. After resetting a burst size according to a state of the data destination, another portion of the data corresponding to the reset burst size is second-transmitted to the data destination. If all the data are not transmitted through the first-transmission and the second-transmission, the second-transmission is repeated until all the data are transmitted. If all the data are transmitted through the first-transmission and the second-transmission, an interrupt signal is generated. Therefore, interrupt signals can be less generated, and thus the processor can access an external memory less frequently, thereby increasing system performance.

    摘要翻译： 提供一种用于控制直接存储器访问的方法和装置。 在该方法中，响应于直接存储器访问控制器（DMAC）操作请求来读取和存储要发送的数据，并且首先将与初始突发大小相对应的数据的一部分发送到数据目的地。 在根据数据目的地的状态复位突发大小之后，与复位突发大小对应的数据的另一部分被第二次发送到数据目的地。 如果所有的数据都不是通过第一次传输和第二次传输传输的，那么重复第二次传输，直到所有的数据被发送。 如果通过第一次传输和第二次传输传输所有数据，则产生一个中断信号。 因此，可以较少地产生中断信号，因此处理器可以较少地访问外部存储器，从而提高系统性能。

    Concurrent write duplex device
    6.
    发明授权
    Concurrent write duplex device 失效
    并发写双工器件

    公开(公告)号：US06389554B1

    公开(公告)日：2002-05-14

    申请号：US09210522

    申请日：1998-12-11

    申请人： Woo Sug Jung ,  Kwang Sug Song ,  Bo Sub Kwon

    发明人： Woo Sug Jung ,  Kwang Sug Song ,  Bo Sub Kwon

    IPC分类号： G06F1100

    CPC分类号： G06F11/2043 ,  G06F11/2097

    摘要： A concurrent write duplexing device with extension of memory bus according to the present invention includes: a primary memory having a first memory in which changed information is stored and a first memory controller for controlling the first memory; a secondary memory having a second memory in which the operating system is loaded to change an operation mode from the standby module to the active module upon failure of duplexing separation and a second memory controller for controlling the second memory; a bus transceiver part for exchanging data with a CPU through a system bus and having a bus transceiver in the first memory controller and a bus transceiver in the second memory controller, to thereby determine as to whether the first and second memory controller operate; and a memory switch part for exchanging data between the active module and the standby module and having memory switches which set direction of memory bus in accordance with an operation mode of module, so that write operation performed in the memory controller of the active module will be executed in the standby module with the same contents and a memory switch controller for controlling the memory switches.

    摘要翻译： 根据本发明的具有扩展存储器总线的并行写双工设备包括：主存储器，其中存储有改变的信息的第一存储器和用于控制第一存储器的第一存储器控制器; 具有第二存储器的辅助存储器，其中加载操作系统以在双工分离失败时将待机模块的操作模式改变为活动模块;以及用于控制第二存储器的第二存储器控制器; 总线收发器部分，用于通过系统总线与CPU交换数据，并且在第一存储器控制器中具有总线收发器，并且在第二存储器控制器中具有总线收发器，从而确定第一和第二存储器控制器是否操作; 以及用于在有源模块和备用模块之间交换数据的存储器开关部件，并具有根据模块的操作模式设置存储器总线的方向的存储器开关，使得在有源模块的存储器控​​制器中执行的写操作将是 在具有相同内容的备用模块中执行，以及用于控制存储器开关的存储器切换控制器。

    Apparatus and method for balancing load across multiple packet processing engines
    7.
    发明授权
    Apparatus and method for balancing load across multiple packet processing engines 有权
    用于平衡多个分组处理引擎的负载的装置和方法

    公开(公告)号：US08885646B2

    公开(公告)日：2014-11-11

    申请号：US13323178

    申请日：2011-12-12

    申请人： Hwan-Jo Heo ,  Nam-Seok Ko ,  Woo-Sug Jung ,  Sung-Jin Moon ,  Sung-Kee Noh ,  Jong-Dae Park ,  Byung-Ho Yae

    发明人： Hwan-Jo Heo ,  Nam-Seok Ko ,  Woo-Sug Jung ,  Sung-Jin Moon ,  Sung-Kee Noh ,  Jong-Dae Park ,  Byung-Ho Yae

    IPC分类号： H04L12/28 ,  H04L12/803

    CPC分类号： H04L47/125

    摘要： A distributed packet processing apparatus capable of distributing packet load across a plurality of packet processing engines is provided. The distributed packet processing apparatus includes a plurality of processing engines each configured to process allocated packets, a first tag generating unit configured to allocate an input packet to a processing engine, which has a processing engine index corresponding to a tag index for the input packet, among the plurality of processing engines, a second tag generating unit configured to calculate a tag index for an output packet, and an index conversion unit configure to convert the tag index for the output packet to one processing engine index among a plurality of processing indexes for the plurality of the processing engines and allocates the output packet to a processing engine having the one processing engine index such that loads are distributed among the plurality of processing engines.

    摘要翻译： 提供能够跨多个分组处理引擎分发分组负载的分布式分组处理装置。 分布式分组处理装置包括：处理分配的分组的多个处理引擎，第一标签生成单元，被配置为向处理引擎分配输入分组，处理引擎具有与输入分组的标签索引对应的处理引擎索引， 在所述多个处理引擎中，第二标签生成单元，被配置为计算输出分组的标签索引，以及索引变换单元，其将所述输出分组的标签索引转换为多个处理索引中的多个处理索引， 多个处理引擎，并且将输出分组分配给具有一个处理引擎索引的处理引擎，使得负载分布在多个处理引擎之间。

    High speed data transfer apparatus for duplexing system
    8.
    发明授权
    High speed data transfer apparatus for duplexing system 失效
    用于双工系统的高速数据传输设备

    公开(公告)号：US5974491A

    公开(公告)日：1999-10-26

    申请号：US824035

    申请日：1997-03-26

    申请人： Woo-Sug Jung ,  Ho-Geun Lee ,  Hwan-Geun Yeo ,  Kwang-Sug Song

    发明人： Woo-Sug Jung ,  Ho-Geun Lee ,  Hwan-Geun Yeo ,  Kwang-Sug Song

    IPC分类号： G06F11/20 ,  G06F13/00 ,  H04L1/00

    CPC分类号： G06F11/1658 ,  G06F11/2038

    摘要： A high speed data transfer apparatus includes a data transfer controlling unit for outputting a signal to the standby mode system during the active mode system, and during the standby mode system, reading data and the data information stored in the second storing unit of the active mode system, storing the read contents in the second storing unit of the standby mode system, and transferring a right to a bus use through the local bus of the standby mode system, the signal being used for informing that there exists data to be transferred.

    摘要翻译： 高速数据传送装置包括：数据传送控制单元，用于在主动模式系统期间向待机模式系统输出信号;在待机模式系统期间，读取存储在活动模式的第二存储单元中的数据和数据信息 系统，将读取的内容存储在待机模式系统的第二存储单元中，并通过备用模式系统的本地总线将权限传送到总线使用，该信号用于通知存在要传送的数据。

    PACKET SCHEDULING METHOD AND APPARATUS BASED ON FAIR BANDWIDTH ALLOCATION
    10.
    发明申请
    PACKET SCHEDULING METHOD AND APPARATUS BASED ON FAIR BANDWIDTH ALLOCATION 有权
    基于公平带宽分配的分组调度方法和设备

    公开(公告)号：US20120127859A1

    公开(公告)日：2012-05-24

    申请号：US13301350

    申请日：2011-11-21

    申请人： Nam-Seok KO ,  Jong-Dae PARK ,  Byung-Ho YAE ,  Sung-Kee NOH ,  Woo-Sug JUNG ,  Sung-Jin MOON ,  Hwan-Jo HEO ,  Soon-Seok LEE

    发明人： Nam-Seok KO ,  Jong-Dae PARK ,  Byung-Ho YAE ,  Sung-Kee NOH ,  Woo-Sug JUNG ,  Sung-Jin MOON ,  Hwan-Jo HEO ,  Soon-Seok LEE

    IPC分类号： H04L12/26

    CPC分类号： H04L47/52 ,  H04L47/568 ,  H04L47/58 ,  H04L47/629

    摘要： A packet scheduling method and apparatus which allows multiple flows that require data transmission to the same output port of a network device such as a router to fairly share bandwidth. The packet scheduling method includes calculating an expected time of arrival of a (k+1)-th packet subsequent to a currently input k-th packet of individual flows by use of bandwidth allocated fairly to each of the flows and a length of the k-th packet; in response to the arrival of the (k+1)-th packet, comparing the expected time of arrival of the (k+1)-th packet to an actual time of arrival of the (k+1)-th packet; and scheduling the (k+1)-th packet of each flow according to the comparison result.

    摘要翻译： 一种分组调度方法和装置，其允许需要数据传输到诸如路由器的网络设备的相同输出端口的多个流以公平地共享带宽。 分组调度方法包括通过使用公平分配给每个流的带宽和k的长度来计算当前输入的各个流的第k个分组之后的第（k + 1）个分组的到达时间 第 响应于第（k + 1）个分组的到达，将第（k + 1）个分组的预期到达时间与第（k + 1）个分组的实际到达时间进行比较; 并根据比较结果调度每个流的第（k + 1）个分组。