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公开(公告)号:US20160133702A1
公开(公告)日:2016-05-12
申请号:US14733354
申请日:2015-06-08
Applicant: JAE-HYUN YOO , KWAN-YOUNG KIM , JIN-HYUN NOH , WOO-YEOL MAENG , KEE-MOON CHUN , YONG-WOO JEON
Inventor: JAE-HYUN YOO , KWAN-YOUNG KIM , JIN-HYUN NOH , WOO-YEOL MAENG , KEE-MOON CHUN , YONG-WOO JEON
IPC: H01L29/10 , H01L29/06 , H01L29/36 , H01L27/088 , H01L29/78
CPC classification number: H01L29/1045 , H01L21/823412 , H01L21/823425 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L27/088 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/36 , H01L29/66545 , H01L29/785
Abstract: A semiconductor device includes a substrate having a first conductive type active region, a second conductive type drift region in the active region, a gate covering the active region on the drift region, a gate insulating film disposed between the active region and the gate, a second conductive type drain region in a location spaced apart from the gate in the drift region and having a higher doping concentration than that of the drift region, a first conductive type shallow well region spaced apart from the drain region in the drift region and between the gate and the drain region, and a second conductive type source region formed in the first conductive type shallow well region between the gate and the drain region and having a higher doping concentration than that of the first conductive type shallow well region.
Abstract translation: 半导体器件包括具有第一导电型有源区,有源区中的第二导电型漂移区,覆盖漂移区上的有源区的栅极,配置在有源区和栅之间的栅极绝缘膜, 第二导电型漏极区域,其位于与漂移区域中的栅极间隔开的位置,并且具有比漂移区域更高的掺杂浓度的位置;与漂移区域中的漏极区域间隔开的第一导电类型的浅阱区域, 栅极和漏极区域以及形成在栅极和漏极区域之间的第一导电类型的浅阱区域中并且具有比第一导电类型的浅阱区域更高的掺杂浓度的第二导电型源极区域。
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公开(公告)号:US09437730B2
公开(公告)日:2016-09-06
申请号:US14803265
申请日:2015-07-20
Applicant: Kwan-Young Kim , Jae-Hyun Yoo , Jin-Hyun Noh , Woo-Yeol Maeng , Yong-Woo Jeon
Inventor: Kwan-Young Kim , Jae-Hyun Yoo , Jin-Hyun Noh , Woo-Yeol Maeng , Yong-Woo Jeon
IPC: H01L29/78 , H01L29/06 , H01L29/423 , H01L29/08 , H01L27/088
CPC classification number: H01L27/0886 , H01L23/528 , H01L29/0649 , H01L29/0653 , H01L29/0865 , H01L29/0873 , H01L29/0882 , H01L29/4232 , H01L29/4236 , H01L29/7816 , H01L29/7835 , H01L29/785
Abstract: According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage.
Abstract translation: 根据示例性实施例,半导体器件包括第一鳍片,与第一鳍片分离的第二鳍片和第一鳍片和第二鳍片上的栅极。 门穿过第一鳍和第二鳍。 第一鳍片包括在栅极两侧的第一掺杂区域。 第一掺杂区被配置为具有施加到其上的第一电压。 第二鳍片包括在栅极两侧的第二掺杂区域。 第二掺杂区被配置为具有施加到其上的第二电压。 第二电压不同于第一电压。
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公开(公告)号:US20160149030A1
公开(公告)日:2016-05-26
申请号:US14803265
申请日:2015-07-20
Applicant: Kwan-Young KIM , Jae-Hyun YOO , Jin-Hyun NOH , Woo-Yeol MAENG , Yong-Woo JEON
Inventor: Kwan-Young KIM , Jae-Hyun YOO , Jin-Hyun NOH , Woo-Yeol MAENG , Yong-Woo JEON
IPC: H01L29/78 , H01L27/088 , H01L29/08 , H01L29/06 , H01L29/423
CPC classification number: H01L27/0886 , H01L23/528 , H01L29/0649 , H01L29/0653 , H01L29/0865 , H01L29/0873 , H01L29/0882 , H01L29/4232 , H01L29/4236 , H01L29/7816 , H01L29/7835 , H01L29/785
Abstract: According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage.
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