公开(公告)号：US11923416B2

公开(公告)日：2024-03-05

申请号：US17829581

申请日：2022-06-01

Applicant: SK hynix Inc.

Inventor： Seong-Wan Ryu

IPC: H01L29/78 ,  H01L21/324 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0873 ,  H01L21/324 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes: a substrate; a first source/drain region and a second source/drain region spaced apart from each other by a trench in the substrate; and a gate structure in the trench, wherein the gate structure includes: a gate dielectric layer formed on a bottom and sidewalls of the trench; a first gate electrode positioned in a bottom portion of the trench over the gate dielectric layer; a second gate electrode positioned over the first gate electrode; and a dipole inducing layer formed between the first gate electrode and the second gate electrode and between sidewalls of the second gate electrode and the gate dielectric layer.

公开(公告)号：US20180337230A1

公开(公告)日：2018-11-22

申请号：US16014635

申请日：2018-06-21

Applicant: MaxPower Semiconductor Inc.

Inventor： Mohamed N. Darwish ,  Jun Zeng ,  Richard A. Blanchard

IPC: H01L29/06 ,  H01L29/861 ,  H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/0611 ,  H01L21/26586 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0873 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8611

Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.

公开(公告)号：US10020228B2

公开(公告)日：2018-07-10

申请号：US15357602

申请日：2016-11-21

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L21/8234 ,  H01L27/092 ,  H01L27/088 ,  H01L27/085 ,  H01L27/06 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L27/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/08 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11529 ,  H01L27/11531

CPC classification number: H01L21/823418 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/085 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

公开(公告)号：US20180090488A1

公开(公告)日：2018-03-29

申请号：US15674071

申请日：2017-08-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Juntao Li ,  Geng Wang ,  Qintao Zhang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/823487 ,  H01L29/0873 ,  H01L29/66659 ,  H01L29/66666 ,  H01L29/66681 ,  H01L29/7817 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/78642

Abstract: Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect transistor (VFET) technology, which enables VFET applications to be broadened to include power amplifiers. By providing a combined asymmetric underlapped drain, high current, low subthreshold slope and LDMOS lightly doped drain, high drain resistance and high drain voltage are enabled.

公开(公告)号：US09647069B2

公开(公告)日：2017-05-09

申请号：US14743796

申请日：2015-06-18

Applicant: Infineon Technologies AG

Inventor： Mayank Shrivastava ,  Cornelius Christian Russ ,  Harald Gossner ,  Ramgopal Rao

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L29/45 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/417

CPC classification number: H01L29/1095 ,  H01L21/26513 ,  H01L27/088 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41775 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7842

Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.

公开(公告)号：US09620614B2

公开(公告)日：2017-04-11

申请号：US14036696

申请日：2013-09-25

Applicant: Madhur Bobde

Inventor： Madhur Bobde

IPC: H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66333 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0873 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/8611

Abstract: This invention discloses a semiconductor power device formed in a semiconductor substrate includes rows of multiple horizontal columns of thin layers of alternate conductivity types in a drift region of the semiconductor substrate where each of the thin layers having a thickness to enable a punch through the thin layers when the semiconductor power device is turned on. In a specific embodiment the thickness of the thin layers satisfying charge balance equation q*ND*WN=q*NA*WP and a punch through condition of WP

公开(公告)号：US09236307B2

公开(公告)日：2016-01-12

申请号：US14702571

申请日：2015-05-01

Applicant: Micron Technology, Inc.

Inventor： Michael A. Smith

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L27/115 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L21/823418 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0617 ,  H01L27/085 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11573 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/788 ,  H01L29/792

Abstract: Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.

Abstract translation: 一些实施例包括具有第一和第二晶体管的集成电路 第一晶体管比第二晶体管宽。 第一和第二晶体管分别具有第一和第二有源区。 电介质特征与第一有源区相关联并且分解第一有源区。 第二活性区域不会分解成与第一活性区域相同的程度。 一些实施例包括形成晶体管的方法。 形成第一和第二晶体管的有源区。 第一晶体管的有效面积比第二晶体管的有效面积宽。 电介质特征形成在第一晶体管的有源区中。 第一晶体管的有效面积被分解为与第二晶体管的有效面积不同的程度。 第一和第二晶体管的有源区同时掺杂。

公开(公告)号：US09231084B2

公开(公告)日：2016-01-05

申请号：US14615058

申请日：2015-02-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Harry-Hak-Lay Chuang ,  Lee-Wee Teo ,  Ming Zhu

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/45 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L29/0873 ,  H01L29/41775 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/78 ,  H01L29/7816

Abstract: A method of forming a semiconductor device comprises forming a gate over a substrate. The method also comprises forming a source and a drain on opposite sides of the gate. The source and the drain are formed such that the source and the drain are separated by a channel region beneath the gate. The source and the drain are positioned such that the channel region has a channel width with respect to a surface of the substrate greater than a width of the gate with respect to the surface of the substrate. The method further comprises forming a first silicide over a portion of the source. The method additionally comprises forming a second silicide over a portion of the drain such that the drain has an unsilicided region adjacent to the gate configured to provide a resistive region configured to sustain a voltage load in a high voltage laterally diffused metal oxide semiconductor (LDMOS) application.

Abstract translation: 形成半导体器件的方法包括在衬底上形成栅极。 该方法还包括在栅极的相对侧上形成源极和漏极。 源极和漏极形成为使得源极和漏极由栅极下方的沟道区域分开。 源极和漏极被定位成使得沟道区域相对于衬底的表面具有大于栅极相对于衬底表面的宽度的沟道宽度。 该方法还包括在源的一部分上形成第一硅化物。 该方法还包括在漏极的一部分上形成第二硅化物，使得漏极具有与栅极相邻的非硅化区域，其被配置为提供被配置为维持高压横向扩散的金属氧化物半导体（LDMOS）中的电压负载的电阻区域， 应用。

公开(公告)号：US20150295049A1

公开(公告)日：2015-10-15

申请号：US14648609

申请日：2013-11-21

Applicant: LG INNOTEK CO., LTD.

Inventor： Seok Min Kang ,  Ji Hye Kim ,  Heung Teak Bae

IPC: H01L29/16 ,  H01L33/34 ,  H01L33/02 ,  H01L29/32

CPC classification number: H01L29/1608 ,  H01L21/02378 ,  H01L21/02521 ,  H01L21/02529 ,  H01L29/0619 ,  H01L29/0873 ,  H01L29/32 ,  H01L29/7802 ,  H01L29/872 ,  H01L33/007 ,  H01L33/025 ,  H01L33/32 ,  H01L33/34

Abstract: An epitaxial wafer includes an epitaxial layer disposed on a substrate. The epitaxial layer includes a first semiconductor layer disposed on the substrate and a second semiconductor layer disposed on the first semiconductor layer and having a thickness that is thicker than that of the first semiconductor layer. A surface defect density of the second semiconductor layer is 0.1/cm2 or less.

Abstract translation: 外延晶片包括设置在基板上的外延层。 外延层包括设置在基板上的第一半导体层和设置在第一半导体层上并具有比第一半导体层厚的厚度的第二半导体层。 第二半导体层的表面缺陷密度为0.1 / cm 2以下。

公开(公告)号：US09159791B2

公开(公告)日：2015-10-13

申请号：US13489467

申请日：2012-06-06

Applicant: Wei-Lin Chen ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Chih-Chung Wang

Inventor： Wei-Lin Chen ,  Ke-Feng Lin ,  Chih-Chien Chang ,  Chih-Chung Wang

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L21/225 ,  H01L21/265 ,  H01L29/45

CPC classification number: H01L29/0878 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0873 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/7809

Abstract: A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type surrounding and being adjacent to the first doped region, wherein the conductive region has a concentration higher than the first doped region; a first heavily doped region disposed in the first doped region; a well having a second conductivity type disposed in the deep well; a second heavily doped region disposed in the well; a gate disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region; and a first trench structure and a second trench structure, wherein a depth of the second trench structure is substantially deeper than a depth of the buried layer.

Abstract translation: 半导体器件包括半导体衬底，设置在半导体衬底中的掩埋层; 深井设置在半导体衬底中; 设置在所述深阱中的第一掺杂区，其中所述第一掺杂区接触所述掩埋层; 导电区域，具有围绕并邻近第一掺杂区域的第一导电类型，其中导电区域的浓度高于第一掺杂区域; 设置在所述第一掺杂区域中的第一重掺杂区域; 具有设置在深井中的具有第二导电类型的阱; 设置在井中的第二重掺杂区域; 设置在所述第一重掺杂区域和所述第二重掺杂区域之间的所述半导体衬底上的栅极; 以及第一沟槽结构和第二沟槽结构，其中所述第二沟槽结构的深度比所述掩埋层的深度更深。