公开(公告)号：US20060292784A1

公开(公告)日：2006-12-28

申请号：US11424995

申请日：2006-06-19

Applicant: Woong Sohn ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Tae-ho Cha

Inventor： Woong Sohn ,  Gil-heyun Choi ,  Chang-won Lee ,  Byung-hee Kim ,  Tae-ho Cha

IPC: H01L21/8238

CPC classification number: H01L21/823462 ,  H01L21/321 ,  H01L21/823437 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11531

Abstract: A method of forming an integrated circuit device can include forming a plurality of stacked cell gates in a memory cell region of a semiconductor substrate and a plurality of high-voltage transistor gates in a peripheral circuit region of the semiconductor substrate. The semiconductor substrate including both the plurality of stacked cell gates and the plurality of high-voltage transistor gates is annealed and the annealed semiconductor substrate including both the plurality of stacked cell gates and the plurality of high-voltage transistor gates is plasma oxidized.

Abstract translation: 形成集成电路器件的方法可以包括在半导体衬底的外围电路区域中的半导体衬底的存储单元区域和多个高压晶体管栅极中形成多个堆叠的单元栅极。 包括多个堆叠的单元栅极和多个高压晶体管栅极的半导体基板被退火，并且包括多个堆叠的单元栅极和多个高压晶体管栅极的退火的半导体衬底被等离子体氧化。