公开(公告)号：US07543254B2

公开(公告)日：2009-06-02

申请号：US11530372

申请日：2006-09-08

申请人： Xiaopeng Xu ,  Dipankar Pramanik

发明人： Xiaopeng Xu ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5018

摘要： Roughly described, high-stress volumetric regions of an integrated circuit structure are predicted by first scanning one or more layout layers to identify planar regions of high 2-dimensional stress, and then performing the much more expensive 3-dimensional stress analysis only on volumetric regions corresponding to those planar regions that were found to have high 2-dimensional stress. A windowing method can be used for the 2-dimensional scan, optionally with an overlap region extending slightly into adjacent windows. Very narrow features arising at the edges of an analysis window can be relocated to the edge of the analysis window in order to avoid numerical artifacts.

摘要翻译： 粗略描述，通过首先扫描一个或多个布局层以识别高二维应力的平面区域，然后仅对体积区域执行更昂贵的三维应力分析来预测集成电路结构的高应力体积区域 对应于被发现具有高二维应力的那些平面区域。 可以使用开窗方法进行二维扫描，可选地具有稍微延伸到相邻窗口中的重叠区域。 在分析窗口边缘出现的非常窄的特征可以重新定位到分析窗口的边缘，以避免数字瑕疵。

公开(公告)号：US20130132914A1

公开(公告)日：2013-05-23

申请号：US13740439

申请日：2013-01-14

申请人： James David Sproch ,  Victor Moroz ,  Xiaopeng Xu ,  Aditya Pradeep Karmarkar

发明人： James David Sproch ,  Victor Moroz ,  Xiaopeng Xu ,  Aditya Pradeep Karmarkar

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5009 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  G06F2217/82 ,  H01L21/76898 ,  H01L21/823807 ,  H01L27/0207 ,  H01L29/7845 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

摘要翻译： 粗略地描述，本发明涉及表征，考虑或利用TSV近晶体管引入的应力的方法。 在表征电路时，可以考虑TSV和附近晶体管之间的物理关系。 在不了解TSV和附近晶体管之间的物理关系的情况下导出的布局可以进行修改。 宏单元可以包括TSV和附近晶体管，以及考虑到晶体管和TSV之间的物理关系的宏单元的仿真模型。 宏单元可以包括TSV和附近的晶体管，其中一个晶体管相对于其他晶体管旋转。 IC还可以包括在TSV附近的晶体管，以将通道中的载流子迁移率改变超过先前认为限定禁区的极限。

公开(公告)号：US08362622B2

公开(公告)日：2013-01-29

申请号：US12430008

申请日：2009-04-24

申请人： James David Sproch ,  Victor Moroz ,  Xiaopeng Xu ,  Aditya Pradeep Karmarkar

发明人： James David Sproch ,  Victor Moroz ,  Xiaopeng Xu ,  Aditya Pradeep Karmarkar

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： G06F17/5072 ,  G06F17/5009 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  G06F2217/82 ,  H01L21/76898 ,  H01L21/823807 ,  H01L27/0207 ,  H01L29/7845 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

摘要翻译： 粗略地描述，本发明涉及表征，考虑或利用TSV近晶体管引入的应力的方法。 在表征电路时，可以考虑TSV和附近晶体管之间的物理关系。 在不了解TSV和附近晶体管之间的物理关系的情况下导出的布局可以进行修改。 宏单元可以包括TSV和附近晶体管，以及考虑到晶体管和TSV之间的物理关系的宏单元的仿真模型。 宏单元可以包括TSV和附近的晶体管，其中一个晶体管相对于其他晶体管旋转。 IC还可以包括在TSV附近的晶体管，以将通道中的载流子迁移率改变超过先前认为限定禁区的极限。

公开(公告)号：US07996795B2

公开(公告)日：2011-08-09

申请号：US12429900

申请日：2009-04-24

申请人： Victor Moroz ,  Xiaopeng Xu

发明人： Victor Moroz ,  Xiaopeng Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/5009

摘要： A method, a computer medium storing computer instructions performing a method, and a computer with processor and memory perform stress modeling as follows. The stress model transforms a representation of a material conversion of a first material in the integrated circuit to a second material in the integrated circuit. Prior to the material conversion the first material occupies a first space having a first boundary. After the material conversion the first material and the second material together occupy a second space having a second boundary. The first space and the second space are different. The stress model performed by the computer system transforms the representation of the material conversion of the first material to the second material into: i) the first material occupying the first space having the first boundary, and ii) a strain displacement condition of the first material. The strain displacement condition is determined by a spatial change from the first boundary to the second boundary.

摘要翻译： 一种存储执行方法的计算机指令的计算机介质和具有处理器和存储器的计算机执行以下压力模拟。 应力模型将集成电路中的第一材料的材料转换的表示转换为集成电路中的第二材料。 在材料转换之前，第一材料占据具有第一边界的第一空间。 在材料转换之后，第一材料和第二材料一起占据具有第二边界的第二空间。 第一个空间和第二个空间是不同的。 由计算机系统执行的应力模型将第一材料的材料转换的表示转换为第二材料，其形成为：i）占据具有第一边界的第一空间的第一材料，以及ii）第一材料的应变位移条件 。 应变位移条件由从第一边界到第二边界的空间变化来确定。

公开(公告)号：US20100274376A1

公开(公告)日：2010-10-28

申请号：US12429900

申请日：2009-04-24

申请人： Victor Moroz ,  Xiaopeng Xu

发明人： Victor Moroz ,  Xiaopeng Xu

IPC分类号： G06F19/00

CPC分类号： G06F17/5009

摘要： A method, a computer medium storing computer instructions performing a method, and a computer with processor and memory perform stress modeling as follows. The stress model transforms a representation of a material conversion of a first material in the integrated circuit to a second material in the integrated circuit. Prior to the material conversion the first material occupies a first space having a first boundary. After the material conversion the first material and the second material together occupy a second space having a second boundary. The first space and the second space are different. The stress model performed by the computer system transforms the representation of the material conversion of the first material to the second material into: i) the first material occupying the first space having the first boundary, and ii) a strain displacement condition of the first material. The strain displacement condition is determined by a spatial change from the first boundary to the second boundary.

摘要翻译： 一种存储执行方法的计算机指令的计算机介质和具有处理器和存储器的计算机执行以下压力模拟。 应力模型将集成电路中的第一材料的材料转换的表示转换为集成电路中的第二材料。 在材料转换之前，第一材料占据具有第一边界的第一空间。 在材料转换之后，第一材料和第二材料一起占据具有第二边界的第二空间。 第一个空间和第二个空间是不同的。 由计算机系统执行的应力模型将第一材料的材料转换的表示转换为第二材料，其形成为：i）占据具有第一边界的第一空间的第一材料，以及ii）第一材料的应变位移条件 。 应变位移条件由从第一边界到第二边界的空间变化来确定。

公开(公告)号：US08661387B2

公开(公告)日：2014-02-25

申请号：US13740439

申请日：2013-01-14

申请人： James David Sproch ,  Victor Moroz ,  Xiaopeng Xu ,  Aditya Pradeep Karmarkar

发明人： James David Sproch ,  Victor Moroz ,  Xiaopeng Xu ,  Aditya Pradeep Karmarkar

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5009 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  G06F2217/82 ,  H01L21/76898 ,  H01L21/823807 ,  H01L27/0207 ,  H01L29/7845 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

摘要翻译： 粗略地描述，本发明涉及表征，考虑或利用TSV近晶体管引入的应力的方法。 在表征电路时，可以考虑TSV和附近晶体管之间的物理关系。 在不了解TSV和附近晶体管之间的物理关系的情况下导出的布局可以进行修改。 宏单元可以包括TSV和附近晶体管，以及考虑到晶体管和TSV之间的物理关系的宏单元的仿真模型。 宏单元可以包括TSV和附近的晶体管，其中一个晶体管相对于其他晶体管旋转。 IC还可以包括在TSV附近的晶体管，以将通道中的载流子迁移率改变超过先前认为限定禁区的极限。

公开(公告)号：US20100270597A1

公开(公告)日：2010-10-28

申请号：US12430008

申请日：2009-04-24

申请人： JAMES DAVID SPROCH ,  Victor Moroz ,  Xiaopeng Xu ,  Aditya Pradeep Karmarkar

发明人： JAMES DAVID SPROCH ,  Victor Moroz ,  Xiaopeng Xu ,  Aditya Pradeep Karmarkar

IPC分类号： H01L29/772 ,  G06F17/50 ,  H01L29/06

CPC分类号： G06F17/5072 ,  G06F17/5009 ,  G06F17/5036 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/12 ,  G06F2217/82 ,  H01L21/76898 ,  H01L21/823807 ,  H01L27/0207 ,  H01L29/7845 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

摘要翻译： 粗略地描述，本发明涉及表征，考虑或利用TSV近晶体管引入的应力的方法。 在表征电路时，可以考虑TSV和附近晶体管之间的物理关系。 在不了解TSV和附近晶体管之间的物理关系的情况下导出的布局可以进行修改。 宏单元可以包括TSV和附近晶体管，以及考虑到晶体管和TSV之间的物理关系的宏单元的仿真模型。 宏单元可以包括TSV和附近的晶体管，其中一个晶体管相对于其他晶体管旋转。 IC还可以包括在TSV附近的晶体管，以将通道中的载流子迁移率改变超过先前认为限定禁区的极限。

公开(公告)号：US20080066023A1

公开(公告)日：2008-03-13

申请号：US11530372

申请日：2006-09-08

申请人： Xiaopeng Xu ,  Dipankar Pramanik

发明人： Xiaopeng Xu ,  Dipankar Pramanik

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5018

摘要： Roughly described, high-stress volumetric regions of an integrated circuit structure are predicted by first scanning one or more layout layers to identify planar regions of high 2-dimensional stress, and then performing the much more expensive 3-dimensional stress analysis only on volumetric regions corresponding to those planar regions that were found to have high 2-dimensional stress. A windowing method can be used for the 2-dimensional scan, optionally with an overlap region extending slightly into adjacent windows. Very narrow features arising at the edges of an analysis window can be relocated to the edge of the analysis window in order to avoid numerical artifacts.

摘要翻译： 粗略描述，通过首先扫描一个或多个布局层以识别高二维应力的平面区域，然后仅对体积区域执行更昂贵的三维应力分析来预测集成电路结构的高应力体积区域 对应于被发现具有高二维应力的那些平面区域。 可以使用开窗方法进行二维扫描，可选地具有稍微延伸到相邻窗口中的重叠区域。 在分析窗口边缘出现的非常窄的特征可以重新定位到分析窗口的边缘，以避免数字瑕疵。