Smart impedance matching for high-speed I/O
    1.
    发明授权
    Smart impedance matching for high-speed I/O 有权
    智能阻抗匹配用于高速I / O

    公开(公告)号:US09548734B1

    公开(公告)日:2017-01-17

    申请号:US14998090

    申请日:2015-12-26

    IPC分类号: H03K19/00 H03K19/0175

    CPC分类号: H03K19/0005 H03K19/017545

    摘要: Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite state machine to provide impedance tuning for a driver; and a control block, the control block to provide a feedback loop to check and tune impedance of the driver. The impedance sensing block is to sample an output voltage of the driver to determine whether the impedance of the driver is greater than or less than an impedance of the channel; and the finite state machine is to produce a signal to decrease or increase the impedance of the driver based on the determination whether the impedance of the driver is greater than or less than the impedance of the channel.

    摘要翻译: 实施例通常涉及用于高速I / O的智能阻抗匹配。 在一些实施例中,电路包括阻抗感测块; 有限状态机为驱动器提供阻抗调谐; 和控制块,控制块提供反馈回路来检查和调谐驱动器的阻抗。 阻抗感测块用于对驱动器的输出电压进行采样,以确定驱动器的阻抗是否大于或小于通道的阻抗; 并且有限状态机基于确定驾驶员的阻抗是否大于或小于通道的阻抗来产生信号以减小或增加驾驶员的阻抗。