公开(公告)号：US08872349B2

公开(公告)日：2014-10-28

申请号：US13610780

申请日：2012-09-11

申请人： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

发明人： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及可嵌入封装组件中的桥互连组件的技术和配置。 在一个实施例中，包装组件包括被配置为在第一管芯和第二管芯之间布置电信号的封装衬底和嵌入在封装衬底中并被配置为在第一管芯和第二管芯之间布置电信号的桥， 包括桥接基板，通过桥接基板形成的一个或多个通孔通孔（THV）和布置在桥接基板的表面上的一个或多个走线，以在第一管芯和第二管芯之间布置电信号。 包括迹线和桥互连组件的接地平面的布线特征可以由气隙分开。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20190229056A1

公开(公告)日：2019-07-25

申请号：US16305758

申请日：2016-06-30

申请人： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim ,  Jackie C. Preciado

发明人： Zhiguo Qian ,  Kemal Aygun ,  Dae-Woo Kim ,  Jackie C. Preciado

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/00

摘要： A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.

公开(公告)号：US09240377B2

公开(公告)日：2016-01-19

申请号：US14579073

申请日：2014-12-22

申请人： Zhiguo Qian ,  Kemal Aygun

发明人： Zhiguo Qian ,  Kemal Aygun

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/538 ,  H01L23/528 ,  H01L25/10 ,  H01L23/498

CPC分类号： H01L23/53228 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

摘要： X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.

公开(公告)号：US20140217579A1

公开(公告)日：2014-08-07

申请号：US13977658

申请日：2011-12-31

申请人： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

发明人： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

摘要： Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

摘要翻译： 描述了包括形成互连结构的电子组件和方法。 在一个实施例中，一种装置包括半导体管芯和裸片上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。 该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。 描述和要求保护其他实施例。

公开(公告)号：US20140071646A1

公开(公告)日：2014-03-13

申请号：US13610663

申请日：2012-09-11

申请人： Zhiguo Qian ,  Kemal Aygun

发明人： Zhiguo Qian ,  Kemal Aygun

IPC分类号： H05K1/02 ,  H05K3/46

CPC分类号： H05K1/0228 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/09336 ,  H05K2201/09672 ,  H05K2201/09709 ,  H05K2201/09727 ,  Y10T29/49155

摘要： Certain embodiments relate to routing structures and their formation. In one embodiment a routing structure includes a first region including a first layer comprising alternating signal traces and ground traces separated by a dielectric. The first region also includes a second layer including alternating signal traces and ground traces separated by a dielectric, wherein the second layer signal positioned over the first layer ground traces, and the second layer ground traces positioned over the first layer signal traces. The first region may also include additional layers of alternating signal and ground traces. The first region may also be formed with the ground traces having a width that is larger than that of the signal traces. The routing structure may also include a second region including pads to which the traces are coupled. Other embodiments are described and claimed.

摘要翻译： 某些实施例涉及路由结构及其形成。 在一个实施例中，路由结构包括包括第一层的第一区域，第一层包括交替的信号迹线和由电介质隔开的接地迹线。 第一区域还包括第二层，其包括由电介质隔开的交替信号迹线和接地迹线，其中位于第一层接地迹线上方的第二层信号，以及位于第一层信号迹线上的第二层接地迹线。 第一区域还可以包括交替信号和接地迹线的附加层。 第一区域也可以形成有具有大于信号迹线的宽度的接地迹线。 路由结构还可以包括包括跟踪耦合到其上的焊盘的第二区域。 描述和要求保护其他实施例。

公开(公告)号：US20140070380A1

公开(公告)日：2014-03-13

申请号：US13610780

申请日：2012-09-11

申请人： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

发明人： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

摘要： Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及可嵌入封装组件中的桥互连组件的技术和配置。 在一个实施例中，包装组件包括被配置为在第一管芯和第二管芯之间布置电信号的封装衬底和嵌入在封装衬底中并被配置为在第一管芯和第二管芯之间布置电信号的桥， 包括桥接基板，通过桥接基板形成的一个或多个通孔通孔（THV）和布置在桥接基板的表面上的一个或多个走线，以在第一管芯和第二管芯之间布置电信号。 包括迹线和桥互连组件的接地平面的布线特征可以由气隙分开。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09622339B2

公开(公告)日：2017-04-11

申请号：US13610663

申请日：2012-09-11

申请人： Zhiguo Qian ,  Kemal Aygun

发明人： Zhiguo Qian ,  Kemal Aygun

IPC分类号： H05K1/02 ,  H05K3/46 ,  H05K1/11

CPC分类号： H05K1/0228 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/113 ,  H05K3/4644 ,  H05K2201/09336 ,  H05K2201/09672 ,  H05K2201/09709 ,  H05K2201/09727 ,  Y10T29/49155

摘要： Certain embodiments relate to routing structures and their formation. In one embodiment a routing structure includes a first region including a first layer comprising alternating signal traces and ground traces separated by a dielectric. The first region also includes a second layer including alternating signal traces and ground traces separated by a dielectric, wherein the second layer signal positioned over the first layer ground traces, and the second layer ground traces positioned over the first layer signal traces. The first region may also include additional layers of alternating signal and ground traces. The first region may also be formed with the ground traces having a width that is larger than that of the signal traces. The routing structure may also include a second region including pads to which the traces are coupled. Other embodiments are described and claimed.

公开(公告)号：US09548734B1

公开(公告)日：2017-01-17

申请号：US14998090

申请日：2015-12-26

申请人： Hongjiang Song ,  Yan W. Song ,  Zhiguo Qian ,  Zhichao Zhang

发明人： Hongjiang Song ,  Yan W. Song ,  Zhiguo Qian ,  Zhichao Zhang

IPC分类号： H03K19/00 ,  H03K19/0175

CPC分类号： H03K19/0005 ,  H03K19/017545

摘要： Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite state machine to provide impedance tuning for a driver; and a control block, the control block to provide a feedback loop to check and tune impedance of the driver. The impedance sensing block is to sample an output voltage of the driver to determine whether the impedance of the driver is greater than or less than an impedance of the channel; and the finite state machine is to produce a signal to decrease or increase the impedance of the driver based on the determination whether the impedance of the driver is greater than or less than the impedance of the channel.

摘要翻译： 实施例通常涉及用于高速I / O的智能阻抗匹配。 在一些实施例中，电路包括阻抗感测块; 有限状态机为驱动器提供阻抗调谐; 和控制块，控制块提供反馈回路来检查和调谐驱动器的阻抗。 阻抗感测块用于对驱动器的输出电压进行采样，以确定驱动器的阻抗是否大于或小于通道的阻抗; 并且有限状态机基于确定驾驶员的阻抗是否大于或小于通道的阻抗来产生信号以减小或增加驾驶员的阻抗。

公开(公告)号：US09368437B2

公开(公告)日：2016-06-14

申请号：US13977658

申请日：2011-12-31

申请人： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

发明人： Sanka Ganesan ,  Zhiguo Qian ,  Robert L. Sankman ,  Krishna Srinivasan ,  Zhaohui Zhu

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/50 ,  H01L23/538

CPC分类号： H01L23/49811 ,  H01L21/76885 ,  H01L23/50 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/1301 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13687 ,  H01L2224/14132 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81395 ,  H01L2224/81411 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/05042 ,  H01L2924/1434 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/014 ,  H01L2924/00014

摘要： Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

摘要翻译： 描述了包括形成互连结构的电子组件和方法。 在一个实施例中，一种装置包括半导体管芯和裸片上的第一金属凸块，第一金属凸块包括具有第一部分和第二部分的表面。 该设备还包括覆盖表面的第一部分并且使表面的第二部分未被覆盖的耐焊接涂层。 描述和要求保护其他实施例。

公开(公告)号：US20140117552A1

公开(公告)日：2014-05-01

申请号：US13665706

申请日：2012-10-31

申请人： Zhiguo Qian ,  Kemal Aygun

发明人： Zhiguo Qian ,  Kemal Aygun

IPC分类号： H01L23/52

CPC分类号： H01L23/53228 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

摘要： X-line routing arrangements for dense multi-chip-package interconnects are described. In an example, an electronic signal routing structure includes a substrate. A plurality of layers of conductive traces is disposed above the substrate. A first pair of ground traces is disposed in a first of the plurality of layers of conductive traces. A signal trace is disposed in a second of the plurality of layers of conductive traces, below the first layer. A second pair of ground traces is disposed in a third of the plurality of layers of conductive traces, below the first layer. The first and second pairs of ground traces and the signal trace provide an X-pattern routing from a cross-sectional perspective.

摘要翻译： 描述了用于密集多芯片封装互连的X线路由布置。 在一个示例中，电子信号路由结构包括基板。 多个导电迹线层设置在衬底上。 第一对接地迹线设置在多个导电迹线层中的第一层中。 信号迹线设置在多层导电迹线的第二层中，位于第一层下方。 第二对接地迹线设置在多层导电迹线的第三层中，位于第一层下方。 第一和第二对接地迹线和信号迹线从横截面的角度提供X图案布线。