公开(公告)号：US09182640B2

公开(公告)日：2015-11-10

申请号：US13244150

申请日：2011-09-23

申请人： Yangho Bae ,  Osung Seo ,  Je Hyeong Park ,  Sanggab Kim

发明人： Yangho Bae ,  Osung Seo ,  Je Hyeong Park ,  Sanggab Kim

IPC分类号： G02F1/136 ,  G02F1/1343 ,  G02F1/1362

CPC分类号： G02F1/13439 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295

摘要： A display apparatus includes a first insulating substrate on which pixels are arranged and a second insulating substrate facing the first insulating substrate. Each pixel includes a gate electrode disposed on the first insulating substrate, a gate insulating layer disposed on the first insulating substrate to cover the gate electrode, a semiconductor pattern disposed on the gate insulating layer to overlap with the gate electrode, a source electrode and a drain electrode disposed on the semiconductor pattern, a transparent pixel electrode disposed on the gate insulating layer and partially making contact with the drain electrode, a protective layer disposed on the pixel electrode, and a common electrode disposed on the first insulating substrate or the second insulating substrate to form an electric field together with the pixel electrode.

摘要翻译： 显示装置包括其上布置有像素的第一绝缘基板和面向第一绝缘基板的第二绝缘基板。 每个像素包括设置在第一绝缘基板上的栅电极，设置在第一绝缘基板上以覆盖栅电极的栅极绝缘层，设置在栅极绝缘层上以与栅电极重叠的半导体图案，源电极和 设置在所述半导体图案上的漏电极，设置在所述栅绝缘层上并部分地与所述漏电极接触的透明像素电极，设置在所述像素电极上的保护层，以及设置在所述第一绝缘基板上的公共电极或所述第二绝缘体 衬底与像素电极一起形成电场。

公开(公告)号：US20120138938A1

公开(公告)日：2012-06-07

申请号：US13244150

申请日：2011-09-23

申请人： Yangho Bae ,  Osung Seo ,  Je Hyeong Park ,  Sanggab Kim

发明人： Yangho Bae ,  Osung Seo ,  Je Hyeong Park ,  Sanggab Kim

IPC分类号： H01L29/786 ,  H01L33/16

CPC分类号： G02F1/13439 ,  G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295

摘要： A display apparatus includes a first insulating substrate on which pixels are arranged and a second insulating substrate facing the first insulating substrate. Each pixel includes a gate electrode disposed on the first insulating substrate, a gate insulating layer disposed on the first insulating substrate to cover the gate electrode, a semiconductor pattern disposed on the gate insulating layer to overlap with the gate electrode, a source electrode and a drain electrode disposed on the semiconductor pattern, a transparent pixel electrode disposed on the gate insulating layer and partially making contact with the drain electrode, a protective layer disposed on the pixel electrode, and a common electrode disposed on the first insulating substrate or the second insulating substrate to form an electric field together with the pixel electrode.

摘要翻译： 显示装置包括其上布置有像素的第一绝缘基板和面向第一绝缘基板的第二绝缘基板。 每个像素包括设置在第一绝缘基板上的栅电极，设置在第一绝缘基板上以覆盖栅电极的栅极绝缘层，设置在栅极绝缘层上以与栅电极重叠的半导体图案，源电极和 设置在所述半导体图案上的漏电极，设置在所述栅绝缘层上并部分地与所述漏电极接触的透明像素电极，设置在所述像素电极上的保护层，以及设置在所述第一绝缘基板上的公共电极或所述第二绝缘体 衬底与像素电极一起形成电场。

公开(公告)号：US20100244032A1

公开(公告)日：2010-09-30

申请号：US12751136

申请日：2010-03-31

申请人： Pil Sang YUN ,  Byeong-Beom KIM ,  Changoh JEONG ,  Yangho BAE ,  Shigeki TOKUCHI ,  Ryoma TSUKUDA ,  Yoshinori MATSUURA ,  Takashi KUBOTA

发明人： Pil Sang YUN ,  Byeong-Beom KIM ,  Changoh JEONG ,  Yangho BAE ,  Shigeki TOKUCHI ,  Ryoma TSUKUDA ,  Yoshinori MATSUURA ,  Takashi KUBOTA

IPC分类号： H01L29/786 ,  H01L21/283 ,  C22C21/00 ,  C23C14/34

CPC分类号： H01L29/458 ,  C22C21/00 ,  C23C14/16 ,  C23C14/3414 ,  H01L21/2855 ,  H01L29/4908

摘要： An Aluminum-Nickel alloy wiring material includes Aluminum, Nickel, Cerium, and Boron. A thin film transistor includes the Aluminum-Nickel alloy wiring material. A sputtering target comprises Aluminum, Nickel, Cerium and Boron. A method of manufacturing a thin film transistor substrate comprises disposing a thin film transistor on a substrate, wherein the thin film transistor includes a wiring circuit layer comprising Aluminum, Nickel, Cerium, and Boron. The Nickel, Cerium and Boron satisfy the following inequalities; 0.5≦X≦5.0, 0.01≦Y≦1.0, and 0.01≦Z≦1.0, respectively, wherein X represents an atomic percentage of Nickel content, Y represents an atomic percentage of Cerium content, and Z represents an atomic percentage of Boron content.

摘要翻译： 铝 - 镍合金布线材料包括铝，镍，铈和硼。 薄膜晶体管包括铝 - 镍合金布线材料。 溅射靶包括铝，镍，铈和硼。 制造薄膜晶体管基板的方法包括在基板上设置薄膜晶体管，其中薄膜晶体管包括包括铝，镍，铈和硼的布线电路层。 镍，铈和硼满足以下不平等： 其中X表示镍含量的原子百分数，Y表示铈含量的原子百分比，Z表示原子百分数，Z表示原子百分数，X表示原子百分数， 硼含量。