中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

5 records (took 0.012 seconds)

    Performance-aware logic operations for generating masks
    1.
    发明授权
    Performance-aware logic operations for generating masks 有权
    用于生成掩码的性能感知逻辑操作

    公开(公告)号：US08227869B2

    公开(公告)日：2012-07-24

    申请号：US13284594

    申请日：2011-10-28

    Applicant: Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

    Inventor： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

    IPC: H01L21/70 ,  H01L27/088 ,  H01L29/76

    CPC classification number: G06F17/5068 ,  G03F1/36

    Abstract: Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.

    Abstract translation: 通过PMOS器件上的压应力层获得用于PMOS和NMOS器件的应力工程，其中当从顶部向下观察时，压应力层具有多边形的形状，并且其中多边形包括限定在其周边的凹部。 NMOS器件具有拉伸应力层，其中从顶部向下观察时，拉伸应力层具有多边形的形状，其中多边形包括在其周边的突起，突出部延伸到第一应力层的凹部中。 因此，可以在不违反设计规则的情况下改善两种装置的应力性能。

    Performance-aware logic operations for generating masks
    2.
    发明授权
    Performance-aware logic operations for generating masks 有权
    用于生成掩码的性能感知逻辑操作

    公开(公告)号：US08122394B2

    公开(公告)日：2012-02-21

    申请号：US12212088

    申请日：2008-09-17

    Applicant: Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

    Inventor： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

    IPC: G06F17/50 ,  G06F7/66 ,  G06K9/00 ,  H01L21/66

    CPC classification number: G06F17/5068 ,  G03F1/36

    Abstract: A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.

    Abstract translation: 用于形成用于制造电路的掩模的方法包括提供电路的设计，其中电路包括器件; 执行第一逻辑操作以确定用于形成所述设备的第一特征的第一区域; 以及执行第二逻辑操作以将所述第一特征扩展到大于所述第一区域的第二区域。 可以使用第二区域的图案来形成掩模。

    Performance-Aware Logic Operations for Generating Masks
    3.
    发明申请
    Performance-Aware Logic Operations for Generating Masks 有权
    用于生成面具的性能感知逻辑操作

    公开(公告)号：US20100065913A1

    公开(公告)日：2010-03-18

    申请号：US12212088

    申请日：2008-09-17

    Applicant: Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

    Inventor： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

    IPC: H01L27/092 ,  G06F17/50

    CPC classification number: G06F17/5068 ,  G03F1/36

    Abstract: A method for forming masks for manufacturing a circuit includes providing a design of the circuit, wherein the circuit comprises a device; performing a first logic operation to determine a first region for forming a first feature of the device; and performing a second logic operation to expand the first feature to a second region greater than the first region. The pattern of the second region may be used to form the masks.

    Abstract translation: 用于形成用于制造电路的掩模的方法包括提供电路的设计，其中电路包括器件; 执行第一逻辑操作以确定用于形成所述设备的第一特征的第一区域; 以及执行第二逻辑操作以将所述第一特征扩展到大于所述第一区域的第二区域。 可以使用第二区域的图案来形成掩模。

    Performance-Aware Logic Operations for Generating Masks
    5.
    发明申请
    Performance-Aware Logic Operations for Generating Masks 有权
    用于生成面具的性能感知逻辑操作

    公开(公告)号：US20120043618A1

    公开(公告)日：2012-02-23

    申请号：US13284594

    申请日：2011-10-28

    Applicant: Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

    Inventor： Lee-Chung Lu ,  Chung-Te Lin ,  Yen-Sen Wang ,  Yao-Jen Chuang ,  Gwan Sin Chang

    IPC: H01L27/092

    CPC classification number: G06F17/5068 ,  G03F1/36

    Abstract: Stress engineering for PMOS and NMOS devices is obtained with a compressive stressor layer over the PMOS device, wherein the compressive stressor layer has the shape of a polygon when viewed from a top down perspective, and wherein the polygon includes a recess defined in its periphery. The NMOS device has a tensile stress layer wherein the tensile stressor layer has the shape of a polygon when viewed from the top down perspective, wherein the polygon includes a protrusion in its periphery, the protrusion extending into the recess of the first stressor layer. Thus, stress performance for both devices can be improved without violating design rules.

    Abstract translation: 通过PMOS器件上的压应力层获得用于PMOS和NMOS器件的应力工程，其中当从顶部向下观察时，压应力层具有多边形的形状，并且其中多边形包括限定在其周边的凹部。 NMOS器件具有拉伸应力层，其中从顶部向下观察时，拉伸应力层具有多边形的形状，其中多边形包括在其周边的突起，突出部延伸到第一应力层的凹部中。 因此，可以在不违反设计规则的情况下改善两种装置的应力性能。

Patent Agency Ranking