公开(公告)号：US07437633B1

公开(公告)日：2008-10-14

申请号：US10402837

申请日：2003-03-27

申请人： Austin H. Lesea ,  Yiding Wu

发明人： Austin H. Lesea ,  Yiding Wu

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31715 ,  G01R31/31726

摘要： Method and apparatus for testing duty cycle at an input/output node is described. A test signal is generated having a non-zero frequency and a duty cycle. The test signal is sampled using a sampling signal. The phase of the sampling signal is shifted to detect a first level change in the sampled test signal. The phase of the sampling signal is then shifted to detect a second level change in the sampled test signal. The duty cycle of the test signal is computed using a phase indicator of the sampling signal at the first level change and a phase indicator of the sampling signal at the second level change.

摘要翻译： 描述了在输入/输出节点处测试占空比的方法和装置。 产生具有非零频率和占空比的测试信号。 使用采样信号对测试信号进行采样。 采样信号的相位被移位以检测采样的测试信号中的第一电平变化。 然后移位采样信号的相位以检测采样的测试信号中的第二电平变化。 使用在第一电平变化时的采样信号的相位指示器来计算测试信号的占空比，并且在第二电平改变时采样信号的相位指示符。

公开(公告)号：US06836864B1

公开(公告)日：2004-12-28

申请号：US10092062

申请日：2002-03-05

申请人： Yiding Wu

发明人： Yiding Wu

IPC分类号： G01R3128

CPC分类号： G01R31/318516 ,  G01R31/31725

摘要： Methods of testing a digital frequency synthesizer (DFS) having a programmable multiplier M and divider D. The full set of tests (wherein every value of M and D is tested) is reduced to a smaller set of tests in which each M/D ratio is tested to a specified resolution. A resolution and minimum and maximum values for M, D, and M/D are specified. An array is allocated, each M/D ratio having a corresponding location in the array, up to the specified resolution. For each MD pair meeting the specified criteria, an M/D ratio is calculated and idealized to the specified resolution, and the MD pair is stored in the corresponding array location. The result is an array of MD pairs that includes zero or one MD pair for each M/D ratio. Thus, by testing each MD pair within the array, all permissible permutations of the input clock frequency are tested.

摘要翻译： 测试具有可编程乘法器M和分频器D的数字频率合成器（DFS）的方法。将全套测试（其中测试M和D的每个值）减少到较小的一组测试，其中每个M / D比 按照指定的分辨率进行测试。 指定了M，D和M / D的分辨率和最小值和最大值。 分配阵列，每个M / D比在阵列中具有相应的位置，直到指定的分辨率。 对于满足指定标准的每个MD对，计算M / D比并将其理想化为指定的分辨率，MD对存储在相应的阵列位置。 结果是对于每个M / D比率的MD对的阵列包括零个或一个MD对。 因此，通过测试阵列内的每个MD对，测试输入时钟频率的所有允许排列。

公开(公告)号：US07864834B1

公开(公告)日：2011-01-04

申请号：US11588774

申请日：2006-10-27

申请人： Yiding Wu

发明人： Yiding Wu

IPC分类号： H04B3/46

CPC分类号： G01R31/31708

摘要： A method of estimating jitter for a DFS can include determining a plurality of linear equations, wherein each linear equation corresponds to, at least in part, a combination of multiplier and divisor attributes for setting an output frequency of the DFS, identifying maximum and minimum values for the slope component and the vertical axis intercept component from the plurality of linear equations, providing an equation for determining minimum jitter given, at least in part, an input frequency, and providing an equation for determining maximum jitter given, at least in part, an input frequency. A linear equation can be derived for estimating jitter of the DFS according to a specified input frequency and a specified value of the divisor attribute of the DFS. The linear equation further can depend upon the minimum jitter and the maximum jitter.

摘要翻译： 估计DFS的抖动的方法可以包括确定多个线性方程，其中每个线性方程至少部分对应于用于设置DFS的输出频率的乘数和除数属性的组合，识别最大值和最小值 对于来自多个线性方程的斜率分量和垂直轴截距分量，提供用于确定至少部分输入频率的最小抖动的方程，并且提供用于确定最大抖动的方程，至少部分地给出， 输入频率。 可以导出线性方程，以根据指定的输入频率和DFS的除数属性的指定值来估计DFS的抖动。 线性方程还可以取决于最小抖动和最大抖动。

公开(公告)号：US07266740B1

公开(公告)日：2007-09-04

申请号：US10977565

申请日：2004-10-29

申请人： Yiding Wu

发明人： Yiding Wu

IPC分类号： G01R31/28

CPC分类号： G01R31/318516 ,  G01R31/31725

摘要： Methods of testing a digital frequency synthesizer (DFS) having a programmable multiplier M and divider D. The full set of tests (wherein every value of M and D is tested) is reduced to a smaller set of tests in which each M/D ratio is tested to a specified resolution. A resolution and minimum and maximum values for M, D, and M/D are specified. An array is allocated, each M/D ratio having a corresponding location in the array, up to the specified resolution. For each MD pair meeting the specified criteria, an M/D ratio is calculated and idealized to the specified resolution, and the MD pair is stored in the corresponding array location. The result is an array of MD pairs that includes zero or one MD pair for each M/D ratio. Thus, by testing each MD pair within the array, all permissible permutations of the input clock frequency are tested.

摘要翻译： 测试具有可编程乘法器M和分频器D的数字频率合成器（DFS）的方法。将全套测试（其中测试M和D的每个值）减少到更小的一组测试，其中每个M / D比 按照指定的分辨率进行测试。 指定了M，D和M / D的分辨率和最小值和最大值。 分配阵列，每个M / D比在阵列中具有相应的位置，直到指定的分辨率。 对于满足指定标准的每个MD对，计算M / D比并将其理想化为指定的分辨率，MD对存储在相应的阵列位置。 结果是对于每个M / D比率的MD对的阵列包括零个或一个MD对。 因此，通过测试阵列内的每个MD对，测试输入时钟频率的所有允许排列。

公开(公告)号：US06329833B1

公开(公告)日：2001-12-11

申请号：US09256964

申请日：1999-02-24

申请人： Yiding Wu

发明人： Yiding Wu

IPC分类号： G01R3126

CPC分类号： G11C29/028 ,  G01R31/3004 ,  G11C29/50 ,  G11C2029/5004

摘要： A measurement system is provided for measuring Vil and Vih of integrated circuits (ICs). The measurement system includes a computer that transmits a control signal to a power supply, which in turn transmits a corresponding applied voltage to the input terminal of an IC. The output terminal of the IC is connected to a parallel port of the computer, thereby forming a feedback loop that allows automatic measurement of Vil and Vih. A method for measuring Vil and Vih utilizing the measurement system includes the steps of transmitting a control signal from a computer to a power supply that causes the power supply to transmit a corresponding applied voltage to the input terminal of the IC, measuring (detecting) a logic level of an output signal transmitted from the IC to the computer, and systematically adjusting the control signal in response to the detected logic level while repeating the steps of transmitting and detecting until the voltage level of the applied voltage is substantially equal to the Vil or the Vih of the IC. In one embodiment, a binary-search approach is utilized to generate the Vil and Vih values in a minimum number of iterations.

摘要翻译： 提供测量系统用于测量集成电路（IC）的Vil和Vih。 测量系统包括将控制信号发送到电源的计算机，电源又将相应的施加的电压传输到IC的输入端。 IC的输出端子连接到计算机的并行端口，从而形成一个允许Vil和Vih自动测量的反馈回路。 利用测量系统测量Vil和Vih的方法包括以下步骤：将控制信号从计算机发送到电源，使电源将相应的施加电压传输到IC的输入端，测量（检测） 从IC发送到计算机的输出信号的逻辑电平，以及响应于检测到的逻辑电平而系统地调整控制信号，同时重复发送和检测的步骤，直到所施加的电压的电压电平基本上等于Vil或 IC的Vih。 在一个实施例中，二进制搜索方法用于以最小迭代次数生成Vil和Vih值。

公开(公告)号：US6167001A

公开(公告)日：2000-12-26

申请号：US237574

申请日：1999-01-26

申请人： Yiding Wu

发明人： Yiding Wu

IPC分类号： G01R29/027 ,  G04F10/00 ,  G04F8/00 ,  G01R31/28 ,  G06F17/50

CPC分类号： G04F10/00 ,  G01R29/0273

摘要： A microelectronic device such as a Field-Programmable Gate Array (FPGA) includes a large number of elements which can be individually configured or programmed to provide a desired logical functionality. Input and output pins enable external connection of the elements. Each element is configurable to produce an output in response to a first pulse which is applied more than a minimum length of time after a second pulse. The first pulse can be a clock pulse, and the second pulse can be a data pulse, in which case the minimum length of time is the setup time for the element. Each element of a device is tested by repeatedly applying first and second pulses to the device with a delay of the second pulse relative to the first pulse being progressively changed from a first value until a second value corresponding to the minimum length of time is reached as indicated by a transition between the output being produced and the output not being produced. The element is then scanned using the first and second pulses and reference pulses with the delay set at the second value to determine the minimum length of time. The scanning procedure can also be used to measure a hold time, a time difference between input and output pulses, or a time difference between two output pulses.

摘要翻译： 诸如现场可编程门阵列（FPGA）的微电子器件包括大量元件，其可被单独配置或编程以提供期望的逻辑功能。 输入和输出引脚可以实现元件的外部连接。 每个元件可配置为响应于在第二脉冲之后被施加大于最小时间长度的第一脉冲而产生输出。 第一个脉冲可以是时钟脉冲，第二个脉冲可以是数据脉冲，在这种情况下，最小时间长度是元件的建立时间。 通过将第一和第二脉冲重复地施加到装置来测试装置的每个元件，其中第二脉冲相对于第一脉冲的延迟从第一值逐渐改变，直到达到对应于最小时间长度的第二个值作为 由正在产生的输出和不产生的输出之间的转换指示。 然后使用第一和第二脉冲和参考脉冲扫描元件，其中延迟设置在第二值以确定最小时间长度。 扫描过程也可用于测量保持时间，输入和输出脉冲之间的时间差或两个输出脉冲之间的时间差。