公开(公告)号：US20050194647A1

公开(公告)日：2005-09-08

申请号：US10793972

申请日：2004-03-05

Applicant: Hung-Chih Tsai ,  Chien-Chih Chou ,  Ying-Ting Chang ,  Che-Jung Chu ,  Kuo-Chio Liu

Inventor： Hung-Chih Tsai ,  Chien-Chih Chou ,  Ying-Ting Chang ,  Che-Jung Chu ,  Kuo-Chio Liu

IPC: H01L31/113

CPC classification number: H01L29/7835 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/456

Abstract: A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.

Abstract translation: 实现了具有改善的击穿电压的高电压PMOS器件。 不对称的高压集成电路结构包括衬底上的栅极电极和位于栅极电极的任一侧和邻近的衬底内的源极和漏极区域，其中源极区域被n阱包围。 对称的高压集成电路结构包括衬底上的栅极电极，位于栅极电极的任一侧和邻近衬底内的源极和漏极区域以及位于栅极电极下方的衬底中的n-阱。 两个结构中的n阱将击穿点从硅表面移动到源极或漏极区域的底部。

公开(公告)号：US07091535B2

公开(公告)日：2006-08-15

申请号：US10793972

申请日：2004-03-05

Applicant: Hung-Chih Tsai ,  Chien-Chih Chou ,  Ying-Ting Chang ,  Che-Jung Chu ,  Kuo-Chio Liu

Inventor： Hung-Chih Tsai ,  Chien-Chih Chou ,  Ying-Ting Chang ,  Che-Jung Chu ,  Kuo-Chio Liu

IPC: H01L29/80

CPC classification number: H01L29/7835 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/456

Abstract: A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.

Abstract translation: 实现了具有改善的击穿电压的高电压PMOS器件。 不对称的高压集成电路结构包括衬底上的栅极电极和位于栅极电极的任一侧和邻近的衬底内的源极和漏极区域，其中源极区域被n阱包围。 对称的高压集成电路结构包括衬底上的栅极电极，位于栅极电极的任一侧和邻近衬底内的源极和漏极区域以及位于栅极电极下方的衬底中的n-阱。 两个结构中的n阱将击穿点从硅表面移动到源极或漏极区域的底部。