公开(公告)号：US09136349B2

公开(公告)日：2015-09-15

申请号：US13345059

申请日：2012-01-06

申请人： Shih-Chi Fu ,  Chien-Chih Chou

发明人： Shih-Chi Fu ,  Chien-Chih Chou

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/762

CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/0207 ,  H01L29/66606

摘要： A structure and method for fabricating a spacer structure for semiconductor devices, such as a multi-gate structure, is provided. The dummy gate structure is formed by depositing a dielectric layer, forming a mask over the dielectric layer, and patterning the dielectric layer. The mask is formed to have a tapered edge. In an embodiment, the tapered edge is formed in a post-patterning process, such as a baking process. In another embodiment, a relatively thick mask layer is utilized such that during patterning a tapered results. The profile of the tapered mask is transferred to the dielectric layer, thereby providing a tapered edge on the dielectric layer.

摘要翻译： 提供了一种用于制造诸如多栅极结构的半导体器件的间隔结构的结构和方法。 虚拟栅极结构通过沉积介电层，在电介质层上形成掩模和图案化电介质层而形成。 掩模形成为具有锥形边缘。 在一个实施例中，锥形边缘在诸如烘烤工艺的后图案化工艺中形成。 在另一个实施例中，使用相对厚的掩模层，使得在图案化期间形成锥形结果。 锥形掩模的轮廓转移到电介质层，从而在电介质层上提供锥形边缘。

公开(公告)号：US08159029B2

公开(公告)日：2012-04-17

申请号：US12256009

申请日：2008-10-22

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L29/76

CPC分类号： H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7835

摘要： A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底中的源极区和漏极区，形成在衬底上的栅极结构，该衬底设置在源极和漏极区之间，第一隔离结构形成在栅极结构和栅极结构之间的衬底中 漏极区域，所述第一隔离结构包括位于所述漏极区域的边缘附近的突起。 每个突起包括在沿着漏极区域的边缘的第一方向上测量的宽度和在垂直于第一方向的第二方向上测量的长度，并且相邻的突起彼此间隔一定距离。

公开(公告)号：US07816744B2

公开(公告)日：2010-10-19

申请号：US12170133

申请日：2008-07-09

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L29/49

CPC分类号： H01L29/4983 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。 栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。 第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

公开(公告)号：US20100096697A1

公开(公告)日：2010-04-22

申请号：US12256009

申请日：2008-10-22

申请人： Ru-Yi Su ,  Pou-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Pou-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L29/78

CPC分类号： H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7835

摘要： A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底中的源极区和漏极区，形成在衬底上的栅极结构，该衬底设置在源极和漏极区之间，第一隔离结构形成在栅极结构和栅极结构之间的衬底中 漏极区域，所述第一隔离结构包括位于所述漏极区域的边缘附近的突起。 每个突起包括在沿着漏极区域的边缘的第一方向上测量的宽度和在垂直于第一方向的第二方向上测量的长度，并且相邻的突起彼此间隔一定距离。

公开(公告)号：US07091535B2

公开(公告)日：2006-08-15

申请号：US10793972

申请日：2004-03-05

申请人： Hung-Chih Tsai ,  Chien-Chih Chou ,  Ying-Ting Chang ,  Che-Jung Chu ,  Kuo-Chio Liu

发明人： Hung-Chih Tsai ,  Chien-Chih Chou ,  Ying-Ting Chang ,  Che-Jung Chu ,  Kuo-Chio Liu

IPC分类号： H01L29/80

CPC分类号： H01L29/7835 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/456

摘要： A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.

摘要翻译： 实现了具有改善的击穿电压的高电压PMOS器件。 不对称的高压集成电路结构包括衬底上的栅极电极和位于栅极电极的任一侧和邻近的衬底内的源极和漏极区域，其中源极区域被n阱包围。 对称的高压集成电路结构包括衬底上的栅极电极，位于栅极电极的任一侧和邻近衬底内的源极和漏极区域以及位于栅极电极下方的衬底中的n-阱。 两个结构中的n阱将击穿点从硅表面移动到源极或漏极区域的底部。

公开(公告)号：US20060084544A1

公开(公告)日：2006-04-20

申请号：US10964751

申请日：2004-10-15

申请人： Chien-Chih Chou

发明人： Chien-Chih Chou

IPC分类号： F16H47/08

CPC分类号： F16H1/46 ,  F16H25/20 ,  F16H2025/2075 ,  F16H2025/2087 ,  H02K7/06

摘要： A device of an improvement on the structure of linear actuator primarily includes a motor body and an output shaft, and at one end of the motor body fixed a gear case in which two sets of planetary gear trains fitted, by which a sun gear of one of the planetary gear trains is disposed at the top of output shaft; according to the above mentioned structure, the mesh teeth number between planetary gear is more to enhance the efficiency of resisting shocks and absorbing vibrates for attaining the intention of reducing cost, decreasing weight, diminishing volume, and promoting better outlook.

公开(公告)号：US06703282B1

公开(公告)日：2004-03-09

申请号：US10187708

申请日：2002-07-02

申请人： Fu Ji Yang ,  Chun Lin Tsai ,  Chien Chih Chou ,  Ting Jia Hu ,  Sheng Yuan Lin

发明人： Fu Ji Yang ,  Chun Lin Tsai ,  Chien Chih Chou ,  Ting Jia Hu ,  Sheng Yuan Lin

IPC分类号： H01L21336

CPC分类号： H01L29/6656 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/3185

摘要： A method of forming an NMOS device with reduced device degradation, generated during a constant current stress, has been developed. The reduced device degradation is attributed to the use of a high temperature oxide (HTO), layer, used as an underlying component of composite insulator spacers, formed on the sides of the NMOS gate structures. After definition of an insulator capped polycide gate structure a thin, (140 to 160 Angstrom), HTO layer is deposited at a temperature between about 700 to 800° C., followed by the deposition of a silicon nitride layer. Definition of the composite insulator layer, comprised with the underlying, HTO, results in NMOS devices with reduced drain current and reduced transconductance values, when compared to counterparts fabricated with composite insulator spacers formed without the thin, HTO layer featured in this invention.

摘要翻译： 已经开发了在恒定电流应力期间产生的具有降低的器件劣化的NMOS器件的形成方法。 降低的器件劣化归因于使用形成在NMOS栅极结构的侧面上的用作复合绝缘体间隔物的潜在部件的高温氧化物（HTO）层。 在绝缘体封端的多晶硅栅极结构的定义之后，在约700至800℃之间的温度下沉积薄（140至160埃）的HTO层，随后沉积氮化硅层。 与底层的HTO组成的复合绝缘体层的定义导致具有降低的漏极电流和降低的跨导值的NMOS器件与在不具有本发明特征的薄HTO层的复合绝缘体间隔物制造的对应物上相比。

公开(公告)号：US08502326B2

公开(公告)日：2013-08-06

申请号：US12888113

申请日：2010-09-22

申请人： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chien-Chih Chou ,  Chun-Lin Tsai

发明人： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chien-Chih Chou ,  Chun-Lin Tsai

IPC分类号： H01L21/02 ,  H01L21/3205

CPC分类号： H01L21/823462 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

摘要： An integrated circuit structure includes a semiconductor substrate and a high-voltage metal-oxide-semiconductor (HVMOS) device, which includes a first high-voltage well (HVW) region of a first conductivity type in the semiconductor substrate; a drain region of a second conductivity type opposite the first conductivity type in the semiconductor substrate and spaced apart from the first HVW region; a gate dielectric with at least a portion directly over the first HVW region; and a gate electrode over the gate dielectric. The gate dielectric includes a bottom gate oxide region; and a silicon nitride region over the bottom gate oxide region.

摘要翻译： 集成电路结构包括半导体衬底和高电压金属氧化物半导体（HVMOS）器件，其包括在半导体衬底中的第一导电类型的第一高电压阱（HVW）区域; 在所述半导体衬底中与所述第一HVW区间隔开的第二导电类型的与所述第一导电类型相反的漏极区; 栅极电介质，其具有直接在所述第一HVW区域上的至少一部分; 以及在栅极电介质上的栅电极。 栅极电介质包括底部栅极氧化物区域; 以及在底部栅极氧化物区域上方的氮化硅区域。

公开(公告)号：US07714392B2

公开(公告)日：2010-05-11

申请号：US11800503

申请日：2007-05-07

申请人： Chia-Der Chang ,  Yu-Ching Chang ,  Chien-Chih Chou ,  Yi-Tung Yen

发明人： Chia-Der Chang ,  Yu-Ching Chang ,  Chien-Chih Chou ,  Yi-Tung Yen

IPC分类号： H01L23/48

CPC分类号： H01L21/31116 ,  H01L21/0276 ,  H01L27/11 ,  H01L27/1104

摘要： A semiconductor device includes a semiconducting substrate having CMOS transistors thereon. A composite etch stop layer including a lowermost silicon oxynitride portion and an uppermost silicon nitride portion is disposed on the semiconducting substrate including the CMOS transistors. At least one dielectric layer is on the composite etch stop layer. A first contact opening extends to a first level through the composite etch stop layer thickness and a second contact opening extends to a second level deeper than the first level through the composite etch stop layer.

摘要翻译： 半导体器件包括其上具有CMOS晶体管的半导体衬底。 包括最下面的氮氧化硅部分和最上面的氮化硅部分的复合蚀刻停止层设置在包括CMOS晶体管的半导体衬底上。 复合蚀刻停止层上至少有一个介电层。 第一接触开口通过复合蚀刻停止层厚度延伸到第一层，并且第二接触开口通过复合蚀刻停止层延伸到比第一层更深的第二层。

公开(公告)号：US07140998B2

公开(公告)日：2006-11-28

申请号：US10964751

申请日：2004-10-15

申请人： Chien-Chih Chou

发明人： Chien-Chih Chou

IPC分类号： F16H57/08 ,  H02K7/10 ,  H02K7/18 ,  H02K41/00

CPC分类号： F16H1/46 ,  F16H25/20 ,  F16H2025/2075 ,  F16H2025/2087 ,  H02K7/06

摘要： A device of an improvement on the structure of linear actuator primarily includes a motor body and an output shaft, and at one end of the motor body fixed a gear case in which two sets of planetary gear trains fitted, by which a sun gear of one of the planetary gear trains is disposed at the top of output shaft; according to the above mentioned structure, the mesh teeth number between planetary gear is more to enhance the efficiency of resisting shocks and absorbing vibrates for attaining the intention of reducing cost, decreasing weight, diminishing volume, and promoting better outlook.

摘要翻译： 线性致动器结构的改进装置主要包括电动机主体和输出轴，并且在电动机主体的一端固定齿轮箱，其中装有两组行星齿轮系，其中一个太阳齿轮一个 的行星齿轮系设置在输出轴的顶部; 根据上述结构，行星齿轮之间的齿数更多地提高抵抗冲击和吸收振动的效率，以达到降低成本，减轻重量，减小体积和促进更好前景的意图。