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    Memory device with built-in test function and method for controlling the same
    1.
    发明授权
    Memory device with built-in test function and method for controlling the same 有权
    具有内置测试功能的内存设备及其控制方法

    公开(公告)号：US07286422B2

    公开(公告)日：2007-10-23

    申请号：US11146339

    申请日：2005-06-06

    申请人： Kyoji Marumoto ,  Yo Sawamura ,  Tatsuhiko Murata ,  Yoshiaki Suenaga

    发明人： Kyoji Marumoto ,  Yo Sawamura ,  Tatsuhiko Murata ,  Yoshiaki Suenaga

    IPC分类号： G11C7/00 ,  G11C29/00

    CPC分类号： G11C29/44 ,  G11C29/76 ,  G11C2029/1208

    摘要： A test circuit employs hardware to test a memory cell in a memory block. The address of an error cell detected is stored in a first or second error address register. Access made by a processor to the address of the error cell would be detected by a first or second address comparator. Data is then written to a first or second correction register, which serves as an alternative cell, or data is read from one of the registers.

    摘要翻译： 测试电路使用硬件来测试存储器块中的存储器单元。 检测到的错误单元的地址存储在第一或第二错误地址寄存器中。 由处理器对误差单元的地址进行的访问将由第一或第二地址比较器检测。 然后将数据写入第一或第二校正寄存器，该补偿寄存器用作备选单元，或者从寄存器之一读取数据。

    Image Processing Device
    2.
    发明申请
    Image Processing Device 审中-公开
    图像处理装置

    公开(公告)号：US20070271406A1

    公开(公告)日：2007-11-22

    申请号：US10599970

    申请日：2005-04-15

    申请人： Yo Sawamura ,  Tetsuya Takemura

    发明人： Yo Sawamura ,  Tetsuya Takemura

    IPC分类号： G06F13/36

    CPC分类号： G09G5/393 ,  G09G5/395 ,  G09G2340/02

    摘要： An image processing device includes a high-speed bus and a peripheral bus linked via a bus bridge, and connected to the buses are a CPU for carrying out computations and control of image processing, a data transceiving FIFO memory for carrying out transceiving of image compression data with a host device, a frame memory for storing image expansion data from an electronic camera and the like and displaying the data on a display panel, and a compression/expansion circuit for carrying out compression of image expansion data and expansion of image compression data. The CPU and the frame memory are connected to the high-speed bus and the data transceiving FIFO memory is connected to the peripheral bus. The arrangement of the image processing device makes the CPU operate more efficiently to achieve overall increased speed in image processing.

    摘要翻译： 图像处理装置包括通过总线桥连接的高速总线和外围总线，并且连接到总线的是用于执行图像处理的计算和控制的CPU，用于执行图像压缩的收发的数据收发FIFO存储器 与主机设备的数据，用于存储来自电子照相机等的图像扩展数据的帧存储器，以及在显示面板上显示数据;以及压缩/扩展电路，用于执行图像扩展数据的压缩和图像压缩数据的扩展 。 CPU和帧存储器连接到高速总线，数据收发FIFO存储器连接到外设总线。 图像处理装置的布置使得CPU更有效地操作以在图像处理中实现总体增加的速度。

    Circuit which supplies a clock pulse to a microcomputer
    4.
    发明授权
    Circuit which supplies a clock pulse to a microcomputer 失效
    向微型计算机提供时钟脉冲的电路

    公开(公告)号：US5673424A

    公开(公告)日：1997-09-30

    申请号：US748795

    申请日：1996-11-14

    申请人： Yo Sawamura

    发明人： Yo Sawamura

    IPC分类号： G06F1/04 ,  G06F1/24 ,  G06F15/78 ,  H03B5/06 ,  H03B5/32 ,  H03K3/03

    CPC分类号： G06F1/24 ,  H03K3/0307

    摘要： A circuit which supplies a clock pulse to activate the microcomputer includes a sinusoidal wave oscillation circuit. A sinusoidal waveulse converting circuit is provided which converts an oscillation output of the sinusoidal wave oscillation circuit into a clock pulse when the level of the oscillation output exceeds a predetermined value. The clock pulse is supplied to the microcomputer by the converting circuit. The converting circuit includes a first inverter having a threshold value on the high voltage side of the central level of the amplitude of the oscillation output and a second inverter having a threshold value on the low voltage side of the central level of the amplitude. In addition, the converting circuit includes an RS flip flop which generates a clock pulse whose level changes alternately by the outputs of the first and second inverters.

    摘要翻译： 提供用于启动微型计算机的时钟脉冲的电路包括正弦波振荡电路。 提供了一种正弦波/脉冲转换电路，其在振荡输出的电平超过预定值时将正弦波振荡电路的振荡输出转换为时钟脉冲。 时钟脉冲由转换电路提供给微型计算机。 转换电路包括在振荡输出的振幅的中心电平的高压侧具有阈值的第一反相器和在振幅的中心电平的低电压侧具有阈值的第二反相器。 此外，转换电路包括RS触发器，其产生电平由第一和第二反相器的输出交替变化的时钟脉冲。

    Portable communicating apparatus
    5.
    发明申请
    Portable communicating apparatus 审中-公开
    便携式通讯装置

    公开(公告)号：US20060250356A1

    公开(公告)日：2006-11-09

    申请号：US11481474

    申请日：2006-07-06

    申请人： Yo Sawamura

    发明人： Yo Sawamura

    IPC分类号： G09G5/00

    CPC分类号： H04N1/00307 ,  G06F1/1613 ,  G06F1/1616 ,  G06F1/165 ,  G06F1/1684 ,  G06F1/1686 ,  G06F1/1698 ,  H04M1/0214 ,  H04M1/575 ,  H04M1/72522 ,  H04M2250/16 ,  H04M2250/52 ,  H04N1/0044 ,  H04N7/141 ,  H04N2101/00 ,  H04N2201/001 ,  H04N2201/0015 ,  H04N2201/0084

    摘要： A display section A and a body section B including a CPU and serving to carry out a signal processing are connected to each other through a folding section C. The display section of a folding portable apparatus is provided with a display panel 2, a camera 3 and image processing means 27 for receiving photographed image data from the camera, carrying out an image processing and directly supplying display image data to the display section. In the case in which data including the image data are to be supplied from the body section to the display section or from the display section to the body section, a data transmitting/receiving function between the CPU and the image processing means is enabled.

    摘要翻译： 通过折叠部分C将显示部分A和包括CPU并且用于执行信号处理的主体部分B彼此连接。折叠式便携式设备的显示部分设置有显示面板2，照相机3 以及图像处理装置27，用于从相机接收拍摄的图像数据，进行图像处理，并将显示图像数据直接提供给显示部分。 在将包括图像数据的数据从主体部分提供给显示部分或从显示部分提供给主体部分的情况下，CPU和图像处理装置之间的数据发送/接收功能成为可能。

    Circuit for controlling the rotation of a rotating member
    7.
    发明授权
    Circuit for controlling the rotation of a rotating member 失效
    用于控制旋转构件的旋转的电路

    公开(公告)号：US5696642A

    公开(公告)日：1997-12-09

    申请号：US351895

    申请日：1994-12-08

    申请人： Yo Sawamura ,  Toshihiro Tafuru

    发明人： Yo Sawamura ,  Toshihiro Tafuru

    IPC分类号： G11B15/467 ,  G11B15/473 ,  H02P29/00 ,  G11B21/04 ,  G05B19/29 ,  G11B5/52 ,  H02P5/17

    CPC分类号： G11B15/4731 ,  G11B15/4673 ,  Y10S388/912

    摘要： A circuit for controlling a rotating member is provided with an input capture register which reads out the value of a free running counter at a timing of an FG (frequency generated) pulse generated in accordance with a rotation of a rotating member. A central processing unit performs an interrupt operation based on a PG (phase generated) pulse generated in accordance with a rotation of the rotating member and an interrupt operation based on the FG pulse. A pulse width modulation circuit rotates the rotating member by use of a speed error signal and a phase error signal which are obtained by the interrupt operations of the central processing unit. A rotating member driver is also provided. The central processing unit calculates the phase error signal from an output of the input capture register based on an FG pulse generated after the generation of the PG pulse.

    摘要翻译： 用于控制旋转构件的电路设置有输入捕获寄存器，其在根据旋转构件的旋转产生的FG（频率产生）脉冲的定时读出自由运行计数器的值。 中央处理单元基于根据旋转构件的旋转产生的PG（相位产生）脉冲和基于FG脉冲的中断操作来执行中断操作。 脉冲宽度调制电路通过使用通过中央处理单元的中断操作获得的速度误差信号和相位误差信号来旋转旋转构件。 还提供旋转构件驱动器。 中央处理单元基于在生成PG脉冲后产生的FG脉冲从输入捕捉寄存器的输出计算相位误差信号。

    Amplitude limiting amplifier circuit
    8.
    发明授权
    Amplitude limiting amplifier circuit 失效
    幅度限幅放大电路

    公开(公告)号：US5210503A

    公开(公告)日：1993-05-11

    申请号：US821075

    申请日：1992-01-16

    申请人： Yo Sawamura

    发明人： Yo Sawamura

    IPC分类号： H03G11/00 ,  H03G11/02

    CPC分类号： H03G11/02 ,  H03G11/00

    摘要： A MOSFET whose back gate area is independent of a substrate is employed as a level-slicing transistor which is simultaneously used for alternately turning ON and turning OFF four analog switches in accordance with the relation between the voltages of the output terminal and inverted input voltage of the output terminal is limited to V.sub.B .+-.V.sub.th, where V.sub.th is the amplitude at the threshold level of the levelslicing transistor and V.sub.B is the bias voltage.

    摘要翻译： 采用背栅区独立于衬底的MOSFET作为电平切割晶体管，其同时用于根据输出端的电压和反相输入电压之间的关系交替地导通和关断四个模拟开关 输出端子限制为VB +/- Vth，其中Vth是电平晶体管的阈值电平处的幅度，VB是偏置电压。