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17 条记录 (耗时 0.016 秒)

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR LOGIC CIRCUIT DEVICE
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR LOGIC CIRCUIT DEVICE 有权
    半导体器件和半导体逻辑电路器件

    公开(公告)号：US20120146149A1

    公开(公告)日：2012-06-14

    申请号：US13398056

    申请日：2012-02-16

    申请人： Youichi Momiyama

    发明人： Youichi Momiyama

    IPC分类号： H01L27/092

    CPC分类号： H01L27/0207 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092

    摘要： A semiconductor device includes two Dt-MOS transistors each having insulation regions respectively under the source and drain regions, the two Dt-MOS transistors sharing a diffusion region as a source region of one Dt-MOS transistor and a drain region of the other Dt-MOS transistor, wherein the insulation regions have respective bottom edges located lower than bottom edges of respective body regions of the Dt-MOS transistors, and wherein the bottom edges of the respective body regions are located deeper than respective bottom edges of the source and drain regions of the Dt-MOS transistors.

    摘要翻译： 半导体器件包括两个分别具有源极和漏极区域的绝缘区域的两个Dt-MOS晶体管，两个Dt-MOS晶体管共享扩散区域作为一个Dt-MOS晶体管的源极区域和另一个Dt-MOS晶体管的漏极区域， MOS晶体管，其中所述绝缘区域具有位于比所述Dt-MOS晶体管的各个体区域的底部边缘低的相应底部边缘，并且其中所述各个主体区域的底部边缘位于比所述源极和漏极区域的相应底部边缘更深的位置 的Dt-MOS晶体管。

    Semiconductor device and manufacturing method of the same
    4.
    发明申请
    Semiconductor device and manufacturing method of the same 有权

    公开(公告)号：US20070166907A1

    公开(公告)日：2007-07-19

    申请号：US11714131

    申请日：2007-03-06

    申请人： Youichi Momiyama

    发明人： Youichi Momiyama

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/6659

    摘要： In consideration of an optimum combination of impurities used for the purpose of forming an extension region (13) and a pocket region (11) and further inhibiting impurity diffusion in the extension region (13) when an impurity diffusion layer (21) is formed in a semiconductor device having an nMOS structure, at least phosphorus (P) is used as an impurity in the extension region (13), at least indium (In) is used as an impurity in the pocket region (11), and additionally carbon (C) is used as a diffusion inhibiting substance. Consequently, it is possible to easily and surely realize the scaling down/high integration of elements while improving threshold voltage roll-off characteristics and current drive capability and reducing a drain leakage current especially in the semiconductor device having the nMOS structure, and particularly by making the optimum design of a semiconductor device having a CMOS structure possible, improve device performance and reduce power consumption.

    Semiconductor device and manufacturing method of the same
    6.
    发明申请
    Semiconductor device and manufacturing method of the same 有权
    半导体器件及其制造方法相同

    公开(公告)号：US20050127449A1

    公开(公告)日：2005-06-16

    申请号：US11049694

    申请日：2005-02-04

    申请人： Youichi Momiyama

    发明人： Youichi Momiyama

    IPC分类号： H01L21/265 ,  H01L21/314 ,  H01L21/336 ,  H01L21/471 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/78 ,  H01L29/94

    CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/6659

    摘要： In consideration of an optimum combination of impurities used for the purpose of forming an extension region (13) and a pocket region (11) and further inhibiting impurity diffusion in the extension region (13) when an impurity diffusion layer (21) is formed in a semiconductor device having an nMOS structure, at least phosphorus (P) is used as an impurity in the extension region (13), at least indium (In) is used as an impurity in the pocket region (11), and additionally carbon (C) is used as a diffusion inhibiting substance. Consequently, it is possible to easily and surely realize the scaling down/high integration of elements while improving threshold voltage roll-off characteristics and current drive capability and reducing a drain leakage current especially in the semiconductor device having the nMOS structure, and particularly by making the optimum design of a semiconductor device having a CMOS structure possible, improve device performance and reduce power consumption.

    摘要翻译： 考虑到为了形成延伸区域（13）和袋区域（11）而使用的杂质的最佳组合，并且当形成杂质扩散层（21）时，进一步抑制扩展区域（13）中的杂质扩散 具有nMOS结构的半导体器件，在延伸区域（13）中至少使用磷（P）作为杂质，至少在该口袋区域（11）中使用铟（In）作为杂质，另外还有碳（ C）用作扩散抑制物质。 因此，特别是在具有nMOS结构的半导体器件中，特别是在具有nMOS结构的半导体器件中，可以容易且可靠地实现元件的缩小/高集成度，同时提高阈值电压滚降特性和电流驱动能力并减少漏极漏电流，特别是通过 具有CMOS结构的半导体器件的最佳设计可能，提高器件性能并降低功耗。

    MOS transistor and fabrication method of semiconductor integrated circuit device
    7.
    发明授权
    MOS transistor and fabrication method of semiconductor integrated circuit device 有权
    MOS晶体管及半导体集成电路器件的制造方法

    公开(公告)号：US08981472B2

    公开(公告)日：2015-03-17

    申请号：US13293252

    申请日：2011-11-10

    申请人： Takae Sukegawa ,  Youichi Momiyama

    发明人： Takae Sukegawa ,  Youichi Momiyama

    IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/49

    CPC分类号： H01L29/7816 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

    摘要： A high-voltage MOS transistor has a semiconductor substrate formed with a first well of a first conductivity type in which a drain region and a drift region are formed and a second well of a second, opposite conductivity type in which a source region and a channel region are formed, a gate electrode extends over the substrate from the second well to the first well via a gate insulation film, wherein there is formed a buried insulation film in the drift region underneath the gate insulation film at a drain edge of the gate electrode, there being formed an offset region in the semiconductor substrate between the channel region and the buried insulation film, wherein the resistance of the offset region is reduced in a surface part thereof by being introduced with an impurity element of the first conductivity type with a concentration exceeding the first well.

    摘要翻译： 高压MOS晶体管具有形成有第一导电类型的第一阱的半导体衬底，其中形成漏极区域和漂移区域，并且第二阱具有第二相反导电类型，其中源极区域和沟道 区域形成，栅电极经由栅极绝缘膜从第二阱延伸到衬底上的第一阱，其中在栅极绝缘膜的漏极边缘处的栅极绝缘膜下方的漂移区域中形成掩埋绝缘膜 在沟道区和掩埋绝缘膜之间的半导体衬底中形成偏移区域，其中通过将第一导电类型的杂质元素以浓度引入而在其表面部分减小偏移区域的电阻 超过第一口井。