Phase frequency detector used in digital PLL system
    1.
    发明授权
    Phase frequency detector used in digital PLL system 有权
    数字PLL系统中使用的相位频率检测器

    公开(公告)号:US07382163B2

    公开(公告)日:2008-06-03

    申请号:US10820473

    申请日:2004-04-07

    CPC classification number: H03D13/004

    Abstract: A phase frequency detector includes a phase error detector outputting a phase error signal according to a first input signal and a second input signal; a phase error judgment unit outputting a phase error judgment signal according to the first input signal and the second input signal; and a reset unit outputting a first reset signal to reset the phase error detector, and outputting a second reset signal to reset the phase error judgment unit, according to the phase error judgment signal.

    Abstract translation: 相位频率检测器包括:相位误差检测器,输出根据第一输入信号和第二输入信号的相位误差信号; 相位误差判断单元,根据第一输入信号和第二输入信号输出相位误差判定信号; 以及复位单元,输出第一复位信号以复位相位误差检测器,并且根据相位误差判断信号输出第二复位信号以复位相位误差判断单元。

    METHOD OF ADJUSTING SAMPLING CONDITION OF ANALOG TO DIGITAL CONVERTER AND APPARATUS THEREOF
    2.
    发明申请
    METHOD OF ADJUSTING SAMPLING CONDITION OF ANALOG TO DIGITAL CONVERTER AND APPARATUS THEREOF 有权
    调制模拟数字转换器采样条件及其设备的方法

    公开(公告)号:US20060197692A1

    公开(公告)日:2006-09-07

    申请号:US11306638

    申请日:2006-01-05

    CPC classification number: H03M1/1245

    Abstract: A method of adjusting a sampling condition to generate a sampling clock in an analog to digital converter includes performing an analog to digital conversion on an analog input signal to thereby produce a digital sampled signal having a plurality of samples; calculating a difference value between two adjacent samples in the digital sampled signal; comparing the difference value with a threshold; adding the difference value into a sum of differences value if the difference value is greater than the threshold; and generating the sampling clock for the analog to digital converter according to the sum of differences value.

    Abstract translation: 一种调整采样条件以在模数转换器中产生采样时钟的方法包括对模拟输入信号执行模数转换,从而产生具有多个采样的数字采样信号; 计算数字采样信号中两个相邻采样之间的差值; 将差值与阈值进行比较; 如果所述差值大于所述阈值,则将所述差值加到差值的和中; 并根据差值的和生成模数转换器的采样时钟。

    Method of adjusting sampling condition of analog to digital converter and apparatus thereof
    3.
    发明授权
    Method of adjusting sampling condition of analog to digital converter and apparatus thereof 有权
    调整模数转换器采样条件的方法及其装置

    公开(公告)号:US07218261B2

    公开(公告)日:2007-05-15

    申请号:US11306638

    申请日:2006-01-05

    CPC classification number: H03M1/1245

    Abstract: A method of adjusting a sampling condition to generate a sampling clock in an analog to digital converter includes performing an analog to digital conversion on an analog input signal to thereby produce a digital sampled signal having a plurality of samples; calculating a difference value between two adjacent samples in the digital sampled signal; comparing the difference value with a threshold; adding the difference value into a sum of differences value if the difference value is greater than the threshold; and generating the sampling clock for the analog to digital converter according to the sum of differences value.

    Abstract translation: 一种调整采样条件以在模数转换器中产生采样时钟的方法包括对模拟输入信号执行模数转换,从而产生具有多个采样的数字采样信号; 计算数字采样信号中两个相邻采样之间的差值; 将差值与阈值进行比较; 如果所述差值大于所述阈值,则将所述差值加到差值的和中; 并根据差值的和生成模数转换器的采样时钟。

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