Verifying an IC layout in individual regions and combining results

    公开(公告)号:US20060265675A1

    公开(公告)日:2006-11-23

    申请号:US11134721

    申请日:2005-05-20

    申请人: Yulan Wang

    发明人: Yulan Wang

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across all regions, and the same rule (i.e. the given rule) is executed globally on the merged data. When an entire runset has been executed in all regions individually, and also executed globally on the merged data, the results thereof are all merged together to yield a final result of a complete execution of the entire runset over the entire IC layout. In some embodiments, certain additional data that could not be rule checked due to the presence of boundaries of adjacent regions is propagated between successive rules in each region.

    VERIFYING AN IC LAYOUT IN INDIVIDUAL REGIONS AND COMBINING RESULTS
    2.
    发明申请
    VERIFYING AN IC LAYOUT IN INDIVIDUAL REGIONS AND COMBINING RESULTS 有权
    验证个别地区的IC布局和组合结果

    公开(公告)号:US20100005434A1

    公开(公告)日:2010-01-07

    申请号:US12559478

    申请日:2009-09-14

    申请人: Yulan Wang

    发明人: Yulan Wang

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across all regions, and the same rule (i.e. the given rule) is executed globally on the merged data. When an entire runset has been executed in all regions individually, and also executed globally on the merged data, the results thereof are all merged together to yield a final result of a complete execution of the entire runset over the entire IC layout. In some embodiments, certain additional data that could not be rule checked due to the presence of boundaries of adjacent regions is propagated between successive rules in each region.

    摘要翻译: 当在集成电路的布局的任何给定区域内进行本地执行规则检查时,无论边界如何(以下称为“全局检查”),产生某些数据被全局检查。 在IC布局的每个区域中执行给定规则导致的待全局检查的数据在所有区域中合并,并且在合并的数据上全局执行相同的规则(即,给定的规则)。 当整个运行集已经在所有区域中单独执行,并且在合并的数据上全局执行时,其结果都被合并在一起,以产生整个运行集合在整个IC布局上的完整执行的最终结果。 在一些实施例中,由于相邻区域的边界的存在而不能被规则检查的某些附加数据在每个区域中的连续规则之间传播。

    Wide geometry recognition by using circle-tangent variable spacing model
    4.
    发明授权
    Wide geometry recognition by using circle-tangent variable spacing model 有权
    通过使用圆切线可变间距模型进行宽几何识别

    公开(公告)号:US07281224B2

    公开(公告)日:2007-10-09

    申请号:US10974104

    申请日:2004-10-26

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: Wide geometry can be accurately extracted from the physical layout of an integrated circuit through the use of detection circles having diameters equal to a threshold width. Projection regions in the layout are selected, and for each projection region, a detection circle of a threshold width (diameter) is defined. A trim region within each projection region is defined using the associated detection circle, such that a portion of the trim region boundary exhibits tangency to the detection circle. The trim regions, which represent non-wide portions of the layout, are then removed to generate a wide element layout. Because the detection circle is a rotation-independent geometry, the over-extraction and under-extraction problems associated with conventional wide element extraction methods can be eliminated.

    摘要翻译: 通过使用直径等于阈值宽度的检测圆,可以从集成电路的物理布局中精确地提取宽几何形状。 选择布局中的投影区域,并且对于每个投影区域,定义阈值宽度(直径)的检测圆。 使用相关联的检测圆限定每个投影区域内的修剪区域,使得修剪区域边界的一部分显示与检测圆相切。 然后移除表示布局的非宽部分的修剪区域以生成宽的元素布局。 由于检测圈是旋转独立的几何形状,因此可以消除与常规宽元件提取方法相关的过度提取和欠提取问题。

    Verifying an IC layout in individual regions and combining results
    7.
    发明授权
    Verifying an IC layout in individual regions and combining results 有权
    验证各个地区的IC布局,并结合结果

    公开(公告)号:US07945872B2

    公开(公告)日:2011-05-17

    申请号:US12559478

    申请日:2009-09-14

    申请人: Yulan Wang

    发明人: Yulan Wang

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across all regions, and the same rule (i.e. the given rule) is executed globally on the merged data. When an entire runset has been executed in all regions individually, and also executed globally on the merged data, the results thereof are all merged together to yield a final result of a complete execution of the entire runset over the entire IC layout. In some embodiments, certain additional data that could not be rule checked due to the presence of boundaries of adjacent regions is propagated between successive rules in each region.

    摘要翻译: 当在集成电路的布局的任何给定区域内进行本地执行规则检查时,无论边界如何(以下称为“全局检查”),产生某些数据被全局检查。 在IC布局的每个区域中执行给定规则导致的待全局检查的数据在所有区域中合并,并且在合并的数据上全局执行相同的规则(即,给定的规则)。 当整个运行集已经在所有区域中单独执行,并且在合并的数据上全局执行时,其结果都被合并在一起,以产生整个集成电路布局完整执行整个运行集的最终结果。 在一些实施例中,由于相邻区域的边界的存在而不能被规则检查的某些附加数据在每个区域中的连续规则之间传播。

    Verifying an IC layout in individual regions and combining results
    8.
    发明授权
    Verifying an IC layout in individual regions and combining results 有权
    验证各个地区的IC布局,并结合结果

    公开(公告)号:US07617464B2

    公开(公告)日:2009-11-10

    申请号:US11134721

    申请日:2005-05-20

    申请人: Yulan Wang

    发明人: Yulan Wang

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across all regions, and the same rule (i.e. the given rule) is executed globally on the merged data. When an entire runset has been executed in all regions individually, and also executed globally on the merged data, the results thereof are all merged together to yield a final result of a complete execution of the entire runset over the entire IC layout. In some embodiments, certain additional data that could not be rule checked due to the presence of boundaries of adjacent regions is propagated between successive rules in each region.

    摘要翻译: 当在集成电路的布局的任何给定区域内进行本地执行规则检查时,无论边界如何(以下称为“全局检查”),产生某些数据被全局检查。 在IC布局的每个区域中执行给定规则导致的待全局检查的数据在所有区域中合并,并且在合并的数据上全局执行相同的规则(即,给定的规则)。 当整个运行集已经在所有区域中单独执行,并且在合并的数据上全局执行时,其结果都被合并在一起,以产生整个集成电路布局完整执行整个运行集的最终结果。 在一些实施例中,由于相邻区域的边界的存在而不能被规则检查的某些附加数据在每个区域中的连续规则之间传播。

    Wide geometry recognition by using circle-tangent variable spacing model
    9.
    发明申请
    Wide geometry recognition by using circle-tangent variable spacing model 有权
    通过使用圆切线可变间距模型进行宽几何识别

    公开(公告)号:US20060090148A1

    公开(公告)日:2006-04-27

    申请号:US10974104

    申请日:2004-10-26

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5081

    摘要: Wide geometry can be accurately extracted from the physical layout of an integrated circuit through the use of detection circles having diameters equal to a threshold width. Projection regions in the layout are selected, and for each projection region, a detection circle of a threshold width (diameter) is defined. A trim region within each projection region is defined using the associated detection circle, such that a portion of the trim region boundary exhibits tangency to the detection circle. The trim regions, which represent non-wide portions of the layout, are then removed to generate a wide element layout. Because the detection circle is a rotation-independent geometry, the over-extraction and under-extraction problems associated with conventional wide element extraction methods can be eliminated.

    摘要翻译: 通过使用直径等于阈值宽度的检测圆,可以从集成电路的物理布局中精确地提取宽几何形状。 选择布局中的投影区域,并且对于每个投影区域,定义阈值宽度(直径)的检测圆。 使用相关联的检测圆限定每个投影区域内的修剪区域,使得修剪区域边界的一部分显示与检测圆相切。 然后移除表示布局的非宽部分的修剪区域以生成宽的元素布局。 由于检测圈是旋转独立的几何形状,因此可以消除与常规宽元件提取方法相关的过度提取和欠提取问题。

    Three-dimensional vector processor
    10.
    发明授权
    Three-dimensional vector processor 失效
    三维矢量处理器

    公开(公告)号:US5019968A

    公开(公告)日:1991-05-28

    申请号:US174653

    申请日:1988-03-29

    摘要: A robotics-control processor for performing real-time inverse kinematics and inverse dynamics calculations involving three-dimensional vectors. The processor employs a three-wide register and execution unit architecture, pipelined instructions, and register-to-register data processing to achieve rapid vector calculations. Broadcast buffers for exchanging operands between register files, and operand multiplexing at several levels within the processor allow program operation flexibility. In a preferred embodiment, the processor includes a CORDIC algorithm unit for rapid vector rotation and trigonometric function calculations.

    摘要翻译: 一种用于执行涉及三维向量的实时逆运动学和逆动力学计算的机器人控制处理器。 处理器采用三宽寄存器和执行单元架构,流水线指令和寄存器到寄存器数据处理,以实现快速向量计算。 用于在寄存器文件之间交换操作数的广播缓冲器以及处理器内的多个级别的操作数复用器允许程序操作灵活性。 在优选实施例中,处理器包括用于快速向量旋转和三角函数计算的CORDIC算法单元。