公开(公告)号：US07006401B2

公开(公告)日：2006-02-28

申请号：US10500400

申请日：2002-12-25

申请人： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

发明人： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

IPC分类号： G11C7/00

CPC分类号： G11C11/40603 ,  G11C11/406

摘要： Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.

摘要翻译： 通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。 当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和 输出使能信号REN。 当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。 此后，当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变为“H”电平，刷新请求 被输入到刷新脉冲发生器电路170，并且输出刷新使能信号RERF。

公开(公告)号：US20050047239A1

公开(公告)日：2005-03-03

申请号：US10500400

申请日：2002-12-25

申请人： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

发明人： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40603 ,  G11C11/406

摘要： Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.

摘要翻译： 通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。 当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和 输出使能信号REN。 当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。此后， 当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变成“H”电平，刷新请求被输入到 输出刷新脉冲发生器电路170和刷新使能信号RERF。