公开(公告)号：US07006401B2

公开(公告)日：2006-02-28

申请号：US10500400

申请日：2002-12-25

申请人： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

发明人： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

IPC分类号： G11C7/00

CPC分类号： G11C11/40603 ,  G11C11/406

摘要： Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.

摘要翻译： 通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。 当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和 输出使能信号REN。 当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。 此后，当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变为“H”电平，刷新请求 被输入到刷新脉冲发生器电路170，并且输出刷新使能信号RERF。

公开(公告)号：US20050047239A1

公开(公告)日：2005-03-03

申请号：US10500400

申请日：2002-12-25

申请人： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

发明人： Hiroyuki Takahashi ,  Takuya Hirota ,  Noriaki Komatsu ,  Atsushi Nakagawa ,  Susumu Takano ,  Masahiro Yoshida ,  Yuuji Torige ,  Hideo Inaba

IPC分类号： G11C11/403 ,  G11C11/406 ,  G11C7/00

CPC分类号： G11C11/40603 ,  G11C11/406

摘要： Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.

摘要翻译： 通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。 当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和 输出使能信号REN。 当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。此后， 当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变成“H”电平，刷新请求被输入到 输出刷新脉冲发生器电路170和刷新使能信号RERF。

公开(公告)号：US06944081B2

公开(公告)日：2005-09-13

申请号：US10363298

申请日：2001-08-30

申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Yoshiyuki Katou ,  Hideo Inaba ,  Noriaki Komatsu ,  Takuya Hirota ,  Masahiro Yoshida

发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Yoshiyuki Katou ,  Hideo Inaba ,  Noriaki Komatsu ,  Takuya Hirota ,  Masahiro Yoshida

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S0, S1 are divided into respective four blocks B0˜B3 and B10˜B13. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.

摘要翻译： 提供能够进一步降低刷新操作的功耗的半导体存储器件。 单元阵列S 0，S 1被分成四个块B 0〜B 3和B 10〜B 13。 在通常的读/写操作中，通过指定字线的地址数据，选择单元阵列中的一个，并且在所选择的单元阵列中选择一个块，并且在所选块中还选择一个字线。 在刷新操作中，选择单元阵列之一，同时刷新所选单元阵列中的四个块。 也就是说，从四个块中的每一个中选择相应的一个字线，并且与多个单元阵列刷新时相比，刷新所选择的字线，从而降低功耗。

公开(公告)号：US07054224B2

公开(公告)日：2006-05-30

申请号：US10478369

申请日：2002-05-23

申请人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

发明人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

IPC分类号： G11C8/00

CPC分类号： G11C11/40615 ,  G11C7/1012 ,  G11C7/1051 ,  G11C11/406 ,  G11C11/4096

摘要： The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.

摘要翻译： 本发明提供一种被配置为伪SRAM的非同步半导体存储器件，并且能够放宽对寻址偏移的限制并提高读取速率。 数据锁存电路110将从存储单元读出的数据保存在由读取模式中包含在地址ADD中的拖尾地址指定的存储单元阵列106中。 在地址中包括的列地址A 0，A 1的转换中，多路复用器111基于列地址A 0，A 1顺序地并且不同步地馈送保存在数据锁存电路110中的数据。

公开(公告)号：US20050207214A1

公开(公告)日：2005-09-22

申请号：US11130464

申请日：2005-05-16

申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Hideo Inaba

发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Hideo Inaba

IPC分类号： G06F1/32 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4074 ,  G11C11/00

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/4074 ,  G11C2207/2227 ,  G11C2211/4067

摘要： A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.

摘要翻译： 提供一种半导体存储器件，其有效地减少与刷新操作相关的电路系统的电流消耗。 在刷新操作之间的间隔时间内，控制信号电路2基于内部片选信号SCI控制n沟道晶体管3C，4B处于截止状态，其中n沟道晶体管3 C，4 B连接在与刷新操作（内部降压电路3和升压电路4）相关联的电路系统和地之间，以便分解与刷新操作相关联的电路系统的泄漏路径，以减少 电流泄漏。 在通过触发定时器开始刷新操作的定时，内部芯片选择信号SCI转换到用于向内部降压电路3和升压电路4提供接地电压的高电平。

公开(公告)号：US06947345B2

公开(公告)日：2005-09-20

申请号：US10473656

申请日：2002-03-28

申请人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

发明人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

IPC分类号： G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C7/00

CPC分类号： G11C11/40615 ,  G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A semiconductor memory device is provided, which is capable of effectively reducing a current comsumption caused by a self-refresh operation in a stand-by mode.In the refresh operation in the stand-by mode, under the control by a refresh control circuit 8B, firstly, a suppression is made for current driving abilities of sense amplifiers 70A˜70D provided for amplifying data signals appearing on bit lines, and secondly, an expansion is made of a pulse width of a row enable signal RE, which defines a period of time for selecting word lines WL, and thirdly, parallel activations of plural word lines are made based on the row enable signal RE with the expanded pulse width, thereby reducing the frequency of operations of the circuit system associated with the refresh operations, resulting in a suppression of the current consumption.

摘要翻译： 提供一种半导体存储器件，其能够有效地降低由待机模式中的自刷新操作引起的电流消耗。 在待机模式的刷新操作中，在刷新控制电路8B的控制下，首先抑制用于放大位线上出现的数据信号的读出放大器70A〜70D的电流驱动能力， 其次，扩展行限制信号RE的脉冲宽度，该行允许信号RE定义了用于选择字线WL的时间段，第三，基于行允许信号RE进行多条字线的并行激活， 扩大的脉冲宽度，从而降低与刷新操作相关联的电路系统的操作频率，导致电流消耗的抑制。

公开(公告)号：US07089351B2

公开(公告)日：2006-08-08

申请号：US10479635

申请日：2002-05-28

申请人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Hideo Inaba

发明人： Hiroyuki Takahashi ,  Atsushi Nakagawa ,  Hideo Inaba

IPC分类号： G06F12/16

CPC分类号： G11C11/40603 ,  G11C11/406 ,  G11C11/40615 ,  G11C2211/4067

摘要： A semiconductor memory device is provided for preventing a late-write from disturbing a refresh operation and also for reducing a current consumption in a write cycle with execution of the late-write. Upon a transition of an address ADD, an address transition detector circuit detects this address transition. Upon receipt of a result of detection by the address transition detector circuit, a state control circuit judges an operation to be executed, from an output enable signal /OE and a write enable signal /WE, and then outputs any of a read statement RS, a write statement WS, and a refresh statement FS. According to a clock signal ACLK, input signals such as addresses are taken for executions of operations based on the statements.

摘要翻译： 提供一种半导体存储器件，用于防止后期写入干扰刷新操作，并且还用于通过执行后期写入来减少写周期中的电流消耗。 地址转换检测器电路在地址ADD的转换时检测该地址转换。 一旦状态控制电路接收到由地址转换检测器电路检测到的结果，就从输出使能信号/ OE和写使能信号/ WE判断要执行的操作，然后输出读出的语句RS， 写入语句WS和刷新语句FS。 根据时钟信号ACLK，基于语句执行诸如地址的输入信号来执行操作。

公开(公告)号：US06928020B2

公开(公告)日：2005-08-09

申请号：US10858728

申请日：2004-06-02

申请人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

发明人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

IPC分类号： G11C11/403 ,  G11C7/10 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/408

摘要： A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit (4) receives change of an address (“Address”), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed. And, for late writing at the time of the next write request, the address and the data are taken into register circuits (3, 12) upon the rising edge of the write enable signal (/WE).

摘要翻译： 提供了一种半导体存储器件，其根据SRAM的规范进行操作，并且能够使存储器周期比以前更短，而没有正常访问被刷新的影响延迟。 ATD电路（4）接收地址变更（“Address”），在地址偏移期间经过后，在地址转换检测信号（ATD）中产生单次脉冲。 在写入请求的情况下，写入使能信号（/ WE）在地址偏移周期内被丢弃。 首先，从单触发脉冲的上升沿执行写入或读取，并且在写入的情况下，使用在直接写入请求时呈现的地址和数据执行后期写入。 接下来，在从单触发脉冲的下降沿到后续存储器周期的地址偏移周期完成的时间段期间执行刷新。 并且，对于在下次写请求时的迟写，地址和数据在写使能信号（/ WE）的上升沿被取入寄存器电路（3,12）。

公开(公告)号：US06876592B2

公开(公告)日：2005-04-05

申请号：US10220951

申请日：2001-03-07

申请人： Hiroyuki Takahashi ,  Hideo Inaba ,  Masatoshi Sonoda ,  Yoshiyuki Kato ,  Atsushi Nakagawa

发明人： Hiroyuki Takahashi ,  Hideo Inaba ,  Masatoshi Sonoda ,  Yoshiyuki Kato ,  Atsushi Nakagawa

IPC分类号： G11C11/403 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  G11C11/408 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C11/4087

摘要： A semiconductor memory device capable of accelerating address access and shortening cycle time is provided. A first address decoder (2) and first refresh address decoder (5) respectively decode an external address (Xn) supplied from outside the semiconductor memory device and a refresh address (RXn) used for refreshing within the semiconductor memory device. A multiplexer (8) selects the external address side decode signal (XnDm) or the refresh address side decode signal (XnRm) and outputs the signal as a decode signal (XnMm) based on an external address transmission signal (EXTR) and refresh address transmission signal (RFTR) so that a refresh operation and a read/write operation is performed continuously within one memory cycle. A word driver (10) then decodes decode signals (XnMm, XpMq) selected with multiplexer (8) and so forth, and activates a word line (WLmq).

摘要翻译： 提供能够加速地址访问和缩短周期时间的半导体存储器件。 第一地址解码器（2）和第一刷新地址解码器（5）分别解码从半导体存储器件外部提供的外部地址（Xn）和在半导体存储器件内用于刷新的刷新地址（RXn）。 复用器（8）根据外部地址发送信号（EXTR）和刷新地址发送（EXTR），选择外部地址侧解码信号（XnDm）或刷新地址侧解码信号（XnRm），并输出作为解码信号（XnMm）的信号 信号（RFTR），使得在一个存储器周期内连续地执行刷新操作和读/写操作。 字驱动器（10）然后解码用多路复用器（8）等选择的解码信号（XnMm，XpMq），并激活字线（WLmq）。

公开(公告)号：US06834020B2

公开(公告)日：2004-12-21

申请号：US10257193

申请日：2002-10-09

申请人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

发明人： Hiroyuki Takahashi ,  Hideo Inaba ,  Atsushi Nakagawa

IPC分类号： G11C700

CPC分类号： G11C11/40615 ,  G11C11/406 ,  G11C11/408

摘要： A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit (4) receives change of an address (“Address”), and generates a one shot pulse in an address transition detect signal (ATD) after an address skew period has elapsed. In the case of a write request, a write enable signal (/WE) is dropped within the address skew period. First, writing or reading is performed from the rising edge of the one shot pulse, and, in the case of writing, late writing is performed using the address and the data which were presented at the time of the directly preceding write request. Next, refresh is performed during the period from the falling edge of the one shot pulse until the address skew period of the subsequent memory cycle is completed. And, for late writing at the time of the next write request, the address and the data are taken into register circuits (3, 12) upon the rising edge of the write enable signal (/WE).

摘要翻译： 提供了一种半导体存储器件，其根据SRAM的规范进行操作，并且能够使存储器周期比以前更短，而没有正常访问被刷新的影响延迟。 ATD电路（4）接收地址变更（“Address”），在地址偏移期间经过后，在地址转换检测信号（ATD）中产生单次脉冲。 在写入请求的情况下，写入使能信号（/ WE）在地址偏移周期内被丢弃。 首先，从单触发脉冲的上升沿执行写入或读取，并且在写入的情况下，使用在直接写入请求时呈现的地址和数据执行后期写入。 接下来，在从单触发脉冲的下降沿到后续存储器周期的地址偏移周期完成的时间段期间执行刷新。 并且，对于在下次写请求时的迟写，地址和数据在写使能信号（/ WE）的上升沿被取入寄存器电路（3,12）。