公开(公告)号：US20120239848A1

公开(公告)日：2012-09-20

申请号：US13360746

申请日：2012-01-29

申请人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

发明人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.

摘要翻译： 嵌入式控制器包括微控制器核心，不支持总线仲裁的第一总线接口，第二总线接口和存储器控制电路。 第一总线接口被配置为从中央处理器（CPU）芯片组接收和发送存储器事务。 第二总线接口被配置为与存储器通信并将CPU芯片组的存储器事务传送到存储器和从存储器传送。 存储器控制电路被配置为评估由于经由第一和第二总线接口在CPU芯片组和存储器之间传送的存储器事务而识别微控制器核心经由第二总线接口访问存储器的不足的饥饿状况，以及 在满足饥饿条件时调用预定义的纠正措施。

公开(公告)号：US07865646B1

公开(公告)日：2011-01-04

申请号：US11490008

申请日：2006-07-20

申请人： Ohad Falik ,  Yehezkel Friedman ,  Victor Flachs ,  Yuval Kirschner

发明人： Ohad Falik ,  Yehezkel Friedman ,  Victor Flachs ,  Yuval Kirschner

IPC分类号： G06F12/00

CPC分类号： G06F13/387

摘要： An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.

摘要翻译： 描述了一种改进的系统，用于允许嵌入式控制器和主处理器共享对计算机系统中的模块的访问。 本发明的共享访问系统使得处理器能够对模块进行一次性一次访问，并且由多个处理器对模块的并发访问。 当两个电源之一不提供电源时，使用具有两个电源的内部总线来允许其中一个处理器继续访问。 提供异步时钟以允许增加模块的吞吐量。 还描述了允许嵌入式控制器访问多于一个模块的协议的示例。

公开(公告)号：US07089339B2

公开(公告)日：2006-08-08

申请号：US09810746

申请日：2001-03-16

申请人： Ohad Falik ,  Yehezkel Friedman ,  Victor Flachs ,  Yuval Kirschner

发明人： Ohad Falik ,  Yehezkel Friedman ,  Victor Flachs ,  Yuval Kirschner

IPC分类号： G06F12/00

CPC分类号： G06F13/387

摘要： An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.

公开(公告)号：US08543755B2

公开(公告)日：2013-09-24

申请号：US13360746

申请日：2012-01-29

申请人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

发明人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

IPC分类号： G06F13/36

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.

摘要翻译： 嵌入式控制器包括微控制器核心，不支持总线仲裁的第一总线接口，第二总线接口和存储器控制电路。 第一总线接口被配置为从中央处理器（CPU）芯片组接收和发送存储器事务。 第二总线接口被配置为与存储器通信并将CPU芯片组的存储器事务传送到存储器和从存储器传送。 存储器控制电路被配置为评估由于经由第一和第二总线接口在CPU芯片组和存储器之间传送的存储器事务而识别微控制器核心经由第二总线接口访问存储器的不足的饥饿状况，以及 在满足饥饿条件时调用预定义的纠正措施。