公开(公告)号：US08543755B2

公开(公告)日：2013-09-24

申请号：US13360746

申请日：2012-01-29

申请人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

发明人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

IPC分类号： G06F13/36

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.

摘要翻译： 嵌入式控制器包括微控制器核心，不支持总线仲裁的第一总线接口，第二总线接口和存储器控制电路。 第一总线接口被配置为从中央处理器（CPU）芯片组接收和发送存储器事务。 第二总线接口被配置为与存储器通信并将CPU芯片组的存储器事务传送到存储器和从存储器传送。 存储器控制电路被配置为评估由于经由第一和第二总线接口在CPU芯片组和存储器之间传送的存储器事务而识别微控制器核心经由第二总线接口访问存储器的不足的饥饿状况，以及 在满足饥饿条件时调用预定义的纠正措施。

公开(公告)号：US20120239848A1

公开(公告)日：2012-09-20

申请号：US13360746

申请日：2012-01-29

申请人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

发明人： Moshe Alon ,  Ilia Stolov ,  Erez Naory ,  Nir Tasher ,  Yuval Kirschner ,  Michal Schramm

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met.

摘要翻译： 嵌入式控制器包括微控制器核心，不支持总线仲裁的第一总线接口，第二总线接口和存储器控制电路。 第一总线接口被配置为从中央处理器（CPU）芯片组接收和发送存储器事务。 第二总线接口被配置为与存储器通信并将CPU芯片组的存储器事务传送到存储器和从存储器传送。 存储器控制电路被配置为评估由于经由第一和第二总线接口在CPU芯片组和存储器之间传送的存储器事务而识别微控制器核心经由第二总线接口访问存储器的不足的饥饿状况，以及 在满足饥饿条件时调用预定义的纠正措施。

公开(公告)号：US08688944B2

公开(公告)日：2014-04-01

申请号：US13236673

申请日：2011-09-20

申请人： Moshe Alon ,  Michal Schramm ,  Nir Tasher

发明人： Moshe Alon ,  Michal Schramm ,  Nir Tasher

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F13/1663 ,  Y02D10/14

摘要： An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.

摘要翻译： 嵌入式控制器包括微控制器核心和存储器控制电路。 存储器控制电路经配置以通过第一串行外设接口（SPI）与第一串行外设接口（SPI）进行通信，对于该第一串行外设接口（SPI），不支持总线仲裁，以第一时钟速率通过第二SPI与存储器进行通信 以第二固定时钟速率，通过第一和第二SPI来中继​​CPU芯片组和存储器之间的存储器事务，以识别在第二SPI上没有存储器事务中继的时间间隔，并且从存储器检索用于操作的信息 在确定的时间间隔内的微控制器内核。

公开(公告)号：US20130073810A1

公开(公告)日：2013-03-21

申请号：US13236673

申请日：2011-09-20

申请人： Moshe Alon ,  Michal Schramm ,  Nir Tasher

发明人： Moshe Alon ,  Michal Schramm ,  Nir Tasher

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F13/1663 ,  Y02D10/14

摘要： An embedded controller includes a microcontroller core and memory control circuitry. The memory control circuitry is configured to communicate with a Central Processing Unit (CPU) chipset over a first Serial Peripheral Interface (SPI), for which bus arbitration is not supported, at a first clock rate, to communicate with a memory over a second SPI at a second, fixed clock rate, to relay memory transactions between the CPU chipset and the memory over the first and second SPIs, to identify time intervals in which no memory transactions are relayed on the second SPI and to retrieve from the memory information for operating the microcontroller core during the identified time intervals.

摘要翻译： 嵌入式控制器包括微控制器核心和存储器控制电路。 存储器控制电路经配置以通过第一串行外设接口（SPI）与第一串行外设接口（SPI）进行通信，对于该第一串行外设接口（SPI），不支持总线仲裁，以第一时钟速率通过第二SPI与存储器进行通信 以第二固定时钟速率，通过第一和第二SPI来中继​​CPU芯片组和存储器之间的存储器事务，以识别在第二SPI上没有存储器事务中继的时间间隔，并且从存储器检索用于操作的信息 在确定的时间间隔内的微控制器内核。

公开(公告)号：US20070297893A1

公开(公告)日：2007-12-27

申请号：US11475223

申请日：2006-06-27

申请人： Moshe Alon ,  Nir Tasher ,  Lior Albaz

发明人： Moshe Alon ,  Nir Tasher ,  Lior Albaz

IPC分类号： F04D15/00 ,  H05K7/20

CPC分类号： F04D27/004 ,  F04D25/166 ,  H05K7/20209

摘要： Methods and systems for controlling the speed of a fan for an electronic system. In some embodiments of the invention, temperatures are associated with changes in the value of a variable relating to fan speed. In one of these embodiments, there is a range of temperatures where the fan speed is fixed. In one embodiment of the invention, where there is a plurality of temperature readings associated with a fan, the temperature reading which would result in the highest fan speed is operative. In one embodiment of the invention, the fan speed control is capable of automatic self-adjustment.

摘要翻译： 用于控制电子系统风扇速度的方法和系统。 在本发明的一些实施例中，温度与与风扇速度相关的变量的值的变化相关联。 在这些实施例中的一个中，存在风扇速度固定的温度范围。 在本发明的一个实施例中，当存在与风扇相关联的多个温度读数时，将导致最高风扇速度的温度读数是可操作的。 在本发明的一个实施例中，风扇速度控制能够进行自动自调节。

公开(公告)号：US20120209449A1

公开(公告)日：2012-08-16

申请号：US13027395

申请日：2011-02-15

申请人： Moshe Alon

发明人： Moshe Alon

IPC分类号： G05D23/19

CPC分类号： G06F1/206 ,  G05D23/1931

摘要： A method of controlling cooling of a processor, including monitoring at least one parameter of a current status of the processor and determining in which of a plurality of value ranges the at least one parameter of the current status of the processor is located. If the at least one parameter is located in a first range, determining a first desired value for a cooling parameter, based on the processor temperature, using a first method, determining a second desired value for the cooling parameter, based on the processor temperature, using a second method, in which the value of the cooling parameter increases, in a manner indicating more cooling, from a low value for a low processor temperature to a higher value for a higher processor temperature and selecting a value of the cooling parameter as a function of the first and second desired values. If the at least one parameter is located in a second range, selecting a value of the cooling parameter of the processor using a third method, based on the processor temperature. Further controlling a cooling unit of the processor according to the selected value of the cooling parameter; and repeating periodically the monitoring, range determination, value selection and controlling.

摘要翻译： 一种控制处理器冷却的方法，包括监视处理器的当前状态的至少一个参数，并确定处理器的当前状态的至少一个参数在多个值范围中的哪一个。 如果至少一个参数位于第一范围内，则使用第一方法，基于处理器温度确定冷却参数的第一期望值，基于处理器温度确定冷却参数的第二期望值， 使用第二种方法，其中冷却参数的值以指示更多冷却的方式从较低的处理器温度的较低值增加到较高的处理器温度值，并且将冷却参数的值选择为 第一和第二期望值的函数。 如果至少一个参数位于第二范围内，则基于处理器温度，使用第三种方法来选择处理器的冷却参数的值。 根据冷却参数的选定值进一步控制处理器的冷却单元; 并定期重复监控，范围确定，价值选择和控制。

公开(公告)号：US07242223B1

公开(公告)日：2007-07-10

申请号：US10797478

申请日：2004-03-10

申请人： Moshe Alon

发明人： Moshe Alon

IPC分类号： H03K9/06

CPC分类号： G04D7/1207

摘要： A frequency monitor circuit (FMC) that is part of an integrated circuit chip for monitoring the frequency of one or more clocks present on the chip is disclosed. The FMC includes a reference window generator, operative to output a reference window signal of a given duration, and a clock counter, operative to count all pulses, in any one of the clocks, that occur within the duration of the reference window and to output a corresponding pulse count. The FMC further includes two or more comparators, each operative to compare the pulse count with a respective given threshold value and to output a corresponding indication of frequency deviation. In one configuration, in which the clock is generated on the chip by a frequency multiplier, the reference window generator and the clock counter are shared between the frequency monitor circuit and the frequency multiplier.

摘要翻译： 公开了一种用于监视芯片上存在的一个或多个时钟的频率的集成电路芯片的一部分的频率监视电路（FMC）。 FMC包括参考窗口生成器，用于输出给定持续时间的参考窗口信号，以及时钟计数器，用于计数在参考窗口的持续时间内发生的任何一个时钟内的所有脉冲，并输出 相应的脉冲计数。 FMC还包括两个或更多个比较器，每个比较器用于将脉冲计数与相应的给定阈值进行比较，并输出相应的频率偏差指示。 在通过倍频器在芯片上产生时钟的一种配置中，参考窗口发生器和时钟计数器在频率监视电路和倍频器之间共享。

公开(公告)号：US08594856B2

公开(公告)日：2013-11-26

申请号：US13027395

申请日：2011-02-15

申请人： Moshe Alon

发明人： Moshe Alon

IPC分类号： G06F19/00

CPC分类号： G06F1/206 ,  G05D23/1931

摘要： A method of controlling cooling of a processor, including monitoring at least one parameter of a current status of the processor and determining in which of a plurality of value ranges the at least one parameter of the current status of the processor is located. If the at least one parameter is located in a first range, determining a first desired value for a cooling parameter, based on the processor temperature, using a first method, determining a second desired value for the cooling parameter, based on the processor temperature, using a second method, in which the value of the cooling parameter increases, in a manner indicating more cooling, from a low value for a low processor temperature to a higher value for a higher processor temperature and selecting a value of the cooling parameter as a function of the first and second desired values. If the at least one parameter is located in a second range, selecting a value of the cooling parameter of the processor using a third method, based on the processor temperature. Further controlling a cooling unit of the processor according to the selected value of the cooling parameter; and repeating periodically the monitoring, range determination, value selection and controlling.

摘要翻译： 一种控制处理器冷却的方法，包括监视处理器的当前状态的至少一个参数，并确定处理器的当前状态的至少一个参数在多个值范围中的哪一个。 如果至少一个参数位于第一范围内，则使用第一方法，基于处理器温度确定冷却参数的第一期望值，基于处理器温度确定冷却参数的第二期望值， 使用第二种方法，其中冷却参数的值以指示更多冷却的方式从较低的处理器温度的较低值增加到较高的处理器温度值，并且将冷却参数的值选择为 第一和第二期望值的函数。 如果至少一个参数位于第二范围内，则基于处理器温度，使用第三种方法来选择处理器的冷却参数的值。 根据冷却参数的选定值进一步控制处理器的冷却单元; 并定期重复监控，范围确定，价值选择和控制。

公开(公告)号：US08549028B1

公开(公告)日：2013-10-01

申请号：US12356985

申请日：2009-01-21

申请人： Moshe Alon ,  Uri Gal

发明人： Moshe Alon ,  Uri Gal

IPC分类号： G06F17/30

CPC分类号： G06Q50/265 ,  G06F17/30424 ,  G06F17/30554 ,  G06F17/3056 ,  G06F17/3087

摘要： Various embodiments of the present invention are related to incident tracking systems and methods. A method allows for receiving input that specifies an incident at a facility, defining a search area adjacent to a position of the incident, and displaying one or more other incidents that occurred at the facility within the search area. A further method allows for dynamically plotting, each time a search area is changed on a map of a facility and an associated date range is indicated, positions on the map within the search area so as to indicate where incidents have occurred at the facility within the date range. Another method allows for receiving input that specifies a name of a person associated with an incident at a facility, and automatically flagging the person as being of interest if the person has been involved in one or more other incidents at the facility.

摘要翻译： 本发明的各种实施例涉及事件追踪系统和方法。 方法允许接收在设施处指定事件的输入，定义与事件位置相邻的搜索区域，以及显示在搜索区域内的设施处发生的一个或多个其他事件。 另一种方法允许动态绘制每次在设施的地图上改变搜索区域并且指示相关联的日期范围时，在搜索区域内的地图上的位置，以便指示在该设施内的事件发生的位置 日期范围。 另一种方法允许接收指定与设施上的事件相关联的人的名称的输入，并且如果该人已经参与在设施处的一个或多个其他事件中，则自动将该人标记为感兴趣。

公开(公告)号：US07178091B1

公开(公告)日：2007-02-13

申请号：US10192761

申请日：2002-07-10

申请人： Moshe Alon

发明人： Moshe Alon

IPC分类号： H03M13/00

CPC分类号： H03M13/159 ,  H03M13/1515 ,  H03M13/158

摘要： An Reed-Solomon encoder and method for block-code encoding by performing a plurality of Galois-Field (GF) multiplication operations utilizing a single GF multiplier. The multiplier generates a set of partial products that are used to calculate all the multiplication operations required for the encoding.

摘要翻译： 一种Reed-Solomon编码器和方法，用于通过使用单个GF乘法器执行多个Galois-Field（GF）乘法运算来进行块编码。 乘数产生一组部分乘积，用于计算编码所需的所有乘法运算。