公开(公告)号：USD993819S1

公开(公告)日：2023-08-01

申请号：US29876578

申请日：2023-05-24

申请人： Zhenghong Wang

设计人： Zhenghong Wang

摘要： FIG. 1 is a front elevation view of a pendant showing the new design;
FIG. 2 is a back elevation view thereof;
FIG. 3 is a left-side view thereof;
FIG. 4 is a right-side view thereof;
FIG. 5 is a top plan view thereof;
FIG. 6 is a bottom plan view thereof;
FIG. 7 is a perspective view thereof;
FIG. 8 is another perspective view thereof; and,
FIG. 9 is an enlarged view of the encircled portion in FIG. 1.
The broken lines depict portions of the article that form no part of the claimed design.

公开(公告)号：USD993818S1

公开(公告)日：2023-08-01

申请号：US29876576

申请日：2023-05-24

申请人： Zhenghong Wang

设计人： Zhenghong Wang

摘要： FIG. 1 is a front elevation view of a pendant showing the new design;
FIG. 2 is a back elevation view thereof;
FIG. 3 is a left-side view thereof;
FIG. 4 is a right-side view thereof;
FIG. 5 is a top plan view thereof;
FIG. 6 is a bottom plan view thereof;
FIG. 7 is a perspective view thereof;
FIG. 8 is another perspective view thereof; and,
FIG. 9 is an enlarged view of the encircled portion in FIG. 1.
The broken lines depict portions of the article that form no part of the claimed design.
The dash-dot-dash boundary lines separate claimed portions of the design from the unclaimed portions of the design. Portions of the design encircled within the dash-dot-dash boundary lines are unclaimed portions of the design. The dash-dot lines are included to show the boundary of the claimed design, and forms no part of the claimed design.

公开(公告)号：USD974949S1

公开(公告)日：2023-01-10

申请号：US29855472

申请日：2022-10-03

申请人： Zhenghong Wang

设计人： Zhenghong Wang

公开(公告)号：US20140267319A1

公开(公告)日：2014-09-18

申请号：US13829461

申请日：2013-03-14

申请人： Ziyad S. HAKURA ,  Zhenghong WANG

发明人： Ziyad S. HAKURA ,  Zhenghong WANG

IPC分类号： G06T1/20

CPC分类号： G06T1/60 ,  G06T15/005

摘要： A tessellation pipeline includes an alpha phase and a beta phase. The alpha phase includes pre-tessellation processing stages, while the beta phase includes post-tessellation processing stages. A processing unit configured to implement a processing stage in the alpha phase stores input graphics data within a buffer and then copies over that buffer with output graphics data, thereby conserving memory resources. The processing unit may also copy output graphics data directly to a level 2 (L2) cache for beta phase processing by other tessellation pipelines, thereby avoiding the need for fixed function copy-out hardware.

摘要翻译： 细分管线包括α相和β相。 α相包括预镶嵌处理阶段，而β阶段包括后镶嵌处理阶段。 配置成实现α相处理阶段的处理单元将输入图形数据存储在缓冲器内，然后通过输出图形数据复制该缓冲器，从而节省存储器资源。 处理单元还可以将输出图形数据直接复制到等级2（L2）高速缓存，以进行其他镶嵌管线的β相处理，从而避免对固定功能复制硬件的需要。

公开(公告)号：US08549208B2

公开(公告)日：2013-10-01

申请号：US12633500

申请日：2009-12-08

申请人： Ruby B. Lee ,  Zhenghong Wang

发明人： Ruby B. Lee ,  Zhenghong Wang

IPC分类号： G06F12/08

CPC分类号： G06F12/128 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0891 ,  G06F2212/1021 ,  Y02B70/30 ,  Y02D10/13

摘要： A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag array storing a plurality of tags corresponding to the plurality of data elements, and an address decoder which permits dynamic memory-to-cache mapping to provide enhanced security of the data elements, as well as enhanced performance. The address decoder receives a context identifier and a plurality of index bits of an address passed to the cache memory, and determines whether a matching value in a line number register exists. The line number registers allow for dynamic memory-to-cache mapping, and their contents can be modified as desired. Methods for accessing and replacing data in a cache memory are also provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received. The plurality of index bits are processed to determine whether a matching index exists in the cache memory and the plurality of tag bits are processed to determine whether a matching tag exists in the cache memory, and a data line is retrieved from the cache memory if both a matching tag and a matching index exist in the cache memory. A random line in the cache memory can be replaced with a data line from a main memory, or evicted without replacement, based on the combination of index and tag misses, security contexts and protection bits. User-defined and/or vendor-defined replacement procedures can be utilized to replace data lines in the cache memory.

摘要翻译： 提供具有增强的性能和安全特征的高速缓冲存储器。 高速缓存存储器包括存储多个数据元素的数据阵列，存储与多个数据元素对应的多个标签的标签阵列，以及允许动态存储器到高速缓存映射以提供数据的增强安全性的地址解码器 元素，以及增强的性能。 地址解码器接收传递给高速缓冲存储器的地址的上下文标识符和多个索引位，并确定是否存在行号寄存器中的匹配值。 行号寄存器允许动态内存到高速缓存映射，并且可以根据需要修改其内容。 还提供了用于访问和替换高速缓冲存储器中的数据的方法，其中接收高速缓冲存储器处的多个索引位和多个标签位。 处理多个索引位以确定高速缓冲存储器中是否存在匹配索引，并且处理多个标签位以确定高速缓冲存储器中是否存在匹配标签，并且如果两者都是从高速缓冲存储器检索数据线 匹配标签和匹配索引存在于高速缓冲存储器中。 高速缓冲存储器中的随机行可以用来自主存储器的数据线替换，或者根据索引和标签未命中，安全上下文和保护位的组合而被驱逐而不需要替换。 可以利用用户定义的和/或供应商定义的替换过程来替代高速缓冲存储器中的数据线。

公开(公告)号：US20100180083A1

公开(公告)日：2010-07-15

申请号：US12633500

申请日：2009-12-08

申请人： Ruby B. Lee ,  Zhenghong Wang

发明人： Ruby B. Lee ,  Zhenghong Wang

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/128 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0864 ,  G06F12/0891 ,  G06F2212/1021 ,  Y02B70/30 ,  Y02D10/13

摘要： A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag array storing a plurality of tags corresponding to the plurality of data elements, and an address decoder which permits dynamic memory-to-cache mapping to provide enhanced security of the data elements, as well as enhanced performance. The address decoder receives a context identifier and a plurality of index bits of an address passed to the cache memory, and determines whether a matching value in a line number register exists. The line number registers allow for dynamic memory-to-cache mapping, and their contents can be modified as desired. Methods for accessing and replacing data in a cache memory are also provided, wherein a plurality of index bits and a plurality of tag bits at the cache memory are received. The plurality of index bits are processed to determine whether a matching index exists in the cache memory and the plurality of tag bits are processed to determine whether a matching tag exists in the cache memory, and a data line is retrieved from the cache memory if both a matching tag and a matching index exist in the cache memory. A random line in the cache memory can be replaced with a data line from a main memory, or evicted without replacement, based on the combination of index and tag misses, security contexts and protection bits. User-defined and/or vendor-defined replacement procedures can be utilized to replace data lines in the cache memory.

摘要翻译： 提供具有增强的性能和安全特征的高速缓冲存储器。 高速缓存存储器包括存储多个数据元素的数据阵列，存储与多个数据元素对应的多个标签的标签阵列，以及允许动态存储器到高速缓存映射以提供数据的增强安全性的地址解码器 元素，以及增强的性能。 地址解码器接收传递给高速缓冲存储器的地址的上下文标识符和多个索引位，并确定是否存在行号寄存器中的匹配值。 行号寄存器允许动态内存到高速缓存映射，并且可以根据需要修改其内容。 还提供了用于访问和替换高速缓冲存储器中的数据的方法，其中接收高速缓冲存储器处的多个索引位和多个标签位。 处理多个索引位以确定高速缓冲存储器中是否存在匹配索引，并且处理多个标签位以确定高速缓冲存储器中是否存在匹配标签，并且如果两者都是从高速缓冲存储器检索数据线 匹配标签和匹配索引存在于高速缓冲存储器中。 高速缓冲存储器中的随机行可以用来自主存储器的数据线替换，或者根据索引和标签未命中，安全上下文和保护位的组合而被驱逐而不需要替换。 可以利用用户定义的和/或供应商定义的替换过程来替代高速缓冲存储器中的数据线。

公开(公告)号：US20090083725A1

公开(公告)日：2009-03-26

申请号：US12081334

申请日：2008-04-15

申请人： Zhenghong Wang

发明人： Zhenghong Wang

IPC分类号： G06F9/44

CPC分类号： G06F8/65

摘要： A firmware upgrading method for an interface card is disclosed. A common interface page under a SES format is established by modifying a microcode control page thereof. More particularly, the claimed method is to upgrade the firmware of an interface driving card of a disk storage system. The preferred embodiment of the present invention includes a step of establishing a common interface page under SES format at first. Next, the step goes to interpret the control page. Next, the information in the control page is extracted. Thereby, the driving card is identified by the extracted information, and further the firmware information is extracted. After that, a processor performs to upgrade the firmware.

摘要翻译： 公开了一种用于接口卡的固件升级方法。 通过修改其微码控制页面来建立SES格式下的公共接口页面。 更具体地，所要求保护的方法是升级盘存储系统的接口驱动卡的固件。 本发明的优选实施例首先包括以SES格式建立公共接口页面的步骤。 接下来，步骤将解释控制页面。 接下来，提取控制页面中的信息。 由此，通过提取的信息来识别驾驶卡，并且进一步提取固件信息。 之后，处理器执行升级固件。