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公开(公告)号：US11809208B2
公开(公告)日：2023-11-07
申请号：US17584314
申请日：2022-01-25
申请人： ABLIC Inc.
发明人： Tsutomu Tomioka
CPC分类号： G05F1/613 , G11C7/1069
摘要： A shunt regulator includes: a capacitor, connected between an output terminal and a ground terminal; a voltage divider circuit and an output transistor, connected between the output terminal and the ground terminal; an error amplifier, controlling the output transistor based on a voltage at an output terminal of the voltage divider circuit and a reference voltage; a non-volatile memory; a memory control circuit, outputting a data read signal to the non-volatile memory; and a voltage detection circuit, detecting that a voltage at the output terminal has reached a predetermined voltage which permits a data reading operation of the non-volatile memory, and outputting a detection signal to the memory control circuit. An operating current of the non-volatile memory is supplied from the capacitor.
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公开(公告)号：US10831219B2
公开(公告)日：2020-11-10
申请号：US16289189
申请日：2019-02-28
申请人： ABLIC Inc.
IPC分类号： G05F1/573 , H02H9/02 , H03K17/082 , H02H1/00
摘要： A voltage regulator includes an error amplifier circuit which controls a gate voltage of an output transistor, an overcurrent protection circuit which prevents an overcurrent of the output transistor, and a protection circuit which detects a negative voltage of an output terminal and controls a gate voltage of the output transistor to suppress an overcurrent. The protection circuit includes a MOS transistor which controls the gate voltage of the output transistor, a clamp circuit connected to a gate of the MOS transistor, a semiconductor element having an N-type region connected to the clamp circuit, and a parasitic bipolar transistor constructed from an N-type region connected to the output terminal as an emitter, a P-type substrate as a base, and the N-type region of the semiconductor element as a collector.
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公开(公告)号：US11662761B2
公开(公告)日：2023-05-30
申请号：US17488331
申请日：2021-09-29
申请人： ABLIC Inc.
发明人： Hideyuki Sawai , Tsutomu Tomioka
摘要： A reference voltage circuit includes: a first and a second NPN transistor having a collector and a base shorted and diode-connected, the second NPN transistor having an emitter connected to a first potential node and operating at a higher current density; a first resistor connected in series with the first NPN transistor; a second resistor having one end connected to a circuit with the first NPN transistor and the first resistor connected in series; a third resistor having one end connected to the collector of the second NPN transistor; a connection point to which the other ends of the second and the third resistor are connected; an arithmetic amplifier circuit having an inverting input terminal, a non-inverting input terminal, and an output terminal respectively connected to the second resistor, the third resistor, and the connection point; and a current supply circuit connected to the collector of the first NPN transistor.
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公开(公告)号：US10591942B2
公开(公告)日：2020-03-17
申请号：US16506733
申请日：2019-07-09
申请人： ABLIC Inc.
摘要： A voltage regulator which includes a differential amplifier circuit containing a first and second input transistors, controlling a gate-source voltage in each of the first and second input transistors including: a current source configured to drive the differential amplifier circuit; the first input transistor containing a gate; the second input transistor containing a gate; and a voltage controller including at least one of a first voltage control circuit to control a voltage at a tail connection point, a second voltage control circuit to control the voltage at the gate of the first input transistor, a third voltage control circuit to control the voltage at the tail connection point, and a fourth voltage control circuit to control the voltage at the gate of the second input transistor.
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公开(公告)号：US20190277908A1
公开(公告)日：2019-09-12
申请号：US16257225
申请日：2019-01-25
申请人： ABLIC Inc.
摘要： A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.
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公开(公告)号：US20190265739A1
公开(公告)日：2019-08-29
申请号：US16249558
申请日：2019-01-16
申请人： ABLIC Inc.
发明人： Tadakatsu Kuroda , Tsutomu Tomioka
摘要： A voltage regulator includes a first switch connected between a first input terminal of an error amplifier circuit and an input terminal of the voltage regulator, a second switch connected between a second input terminal of the error amplifier circuit and an output terminal of the voltage regulator, a third switch connected between the first input terminal and the second input terminal, and a short fault detection circuit which detects a short fault of the output terminal, based on an output voltage of the voltage regulator.
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公开(公告)号：US11025047B2
公开(公告)日：2021-06-01
申请号：US16440600
申请日：2019-06-13
申请人： ABLIC Inc.
发明人： Tsutomu Tomioka , Tadakatsu Kuroda
IPC分类号： H02H9/00 , H02H3/00 , H03K19/0185
摘要： Provided is a backflow prevention circuit including a backflow prevention transistor as a p-channel MOS transistor interposed in series between an input terminal to which a power supply voltage is supplied, and an output-stage transistor as a p-channel MOS transistor, configured to supply an output voltage from an output terminal, and a backflow prevention control circuit configured to turn off the backflow prevention transistor if the output voltage exceeds the power supply voltage. The backflow prevention control circuit includes a first transistor, a first current source circuit, and a level shift circuit.
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公开(公告)号：US11012041B2
公开(公告)日：2021-05-18
申请号：US16444610
申请日：2019-06-18
申请人： ABLIC Inc.
IPC分类号： H03F3/45
摘要： A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.
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公开(公告)号：US10571942B2
公开(公告)日：2020-02-25
申请号：US16240410
申请日：2019-01-04
申请人： ABLIC Inc.
发明人： Tsutomu Tomioka
摘要： The overcurrent limiting circuit includes: a limit voltage generation circuit generating a limit voltage which defines the limit current value as a current corresponding to a magnitude of a power supply voltage; a source follower having an output terminal and an input terminal which is connected to a gate of the output stage transistor, and configured to supply from the output terminal a voltage level-shifted from a voltage provided to the input terminal; an error amplifier circuit amplifying a difference between the limit voltage and the voltage supplied from the source follower; and a gate voltage adjustment transistor having a gate to which the voltage supplied from the error amplifier circuit is applied, and controlling a gate voltage applied to the gate of the output stage transistor.
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公开(公告)号：US10914783B2
公开(公告)日：2021-02-09
申请号：US16257225
申请日：2019-01-25
申请人： ABLIC Inc.
摘要： A test circuit includes a test pad supplied with a test signal causing the test circuit to be transitioned to a test mode, and further includes a first p channel MOS transistor having a source connected to the test pad, and a gate applied with a prescribed reference voltage, a first n channel MOS transistor having a drain connected to a drain of the first p channel MOS transistor, and a source grounded via a first current limiting element, and a control circuit which has an input terminal connected to the drain of the first n channel MOS transistor, and an output terminal connected to a gate of the first n Tr, and controls the first n channel MOS transistor from an on state to an off state when the test signal becomes a prescribed voltage or more.
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