公开(公告)号：US12153927B2

公开(公告)日：2024-11-26

申请号：US16889010

申请日：2020-06-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas Clouqueur ,  Marius Evers ,  Aparna Mandke ,  Steven R. Havlir ,  Robert Cohen ,  Anthony Jarvis

IPC: G06F9/38 ,  G06F9/48

Abstract: Merging branch target buffer entries includes maintaining, in a branch target buffer, an entry corresponding to first branch instruction, where the entry identifies a first branch target address for the first branch instruction and a second branch target address for a second branch instruction; and accessing, based on the first branch instruction, the entry.

公开(公告)号：US11256505B2

公开(公告)日：2022-02-22

申请号：US17169053

申请日：2021-02-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arunachalam Annamalai ,  Marius Evers ,  Aparna Thyagarajan ,  Anthony Jarvis

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3296

Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.

公开(公告)号：US10713054B2

公开(公告)日：2020-07-14

申请号：US16030031

申请日：2018-07-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas Cloqueur ,  Anthony Jarvis

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor includes two or more branch target buffer (BTB) tables for branch prediction, each BTB table storing entries of a different target size or width or storing entries of a different branch type. Each BTB entry includes at least a tag and a target address. For certain branch types that only require a few target address bits, the respective BTB tables are narrower thereby allowing for more BTB entries in the processor separated into respective BTB tables by branch instruction type. An increased number of available BTB entries are stored in a same or a less space in the processor thereby increasing a speed of instruction processing. BTB tables can be defined that do not store any target address and rely on a decode unit to provide it. High value BTB entries have dedicated storage and are therefore less likely to be evicted than low value BTB entries.

公开(公告)号：US11416253B2

公开(公告)日：2022-08-16

申请号：US16926339

申请日：2020-07-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas Clouqueur ,  Anthony Jarvis

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor includes two or more branch target buffer (BTB) tables for branch prediction, each BTB table storing entries of a different target size or width or storing entries of a different branch type. Each BTB entry includes at least a tag and a target address. For certain branch types that only require a few target address bits, the respective BTB tables are narrower thereby allowing for more BTB entries in the processor separated into respective BTB tables by branch instruction type. An increased number of available BTB entries are stored in a same or a less space in the processor thereby increasing a speed of instruction processing. BTB tables can be defined that do not store any target address and rely on a decode unit to provide it. High value BTB entries have dedicated storage and are therefore less likely to be evicted than low value BTB entries.

公开(公告)号：US11216279B2

公开(公告)日：2022-01-04

申请号：US16200491

申请日：2018-11-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony Jarvis ,  Thomas Clouqueur

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: A processor includes a prediction engine coupled to a training engine. The prediction engine includes a loop exit predictor. The training engine includes a loop exit branch monitor coupled to a loop detector. Based on at least one of a plurality of call return levels, the loop detector of the processor takes a snapshot of a retired predicted block during a first retirement time, compares the snapshot to a subsequent retired predicted block at a second retirement time, and based on the comparison, identifies a loop and loop exit branches within the loop for use by the loop exit branch monitor and the loop exit predictor to determine whether to override a general purpose conditional prediction.

公开(公告)号：US10915322B2

公开(公告)日：2021-02-09

申请号：US16134440

申请日：2018-09-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arunachalam Annamalai ,  Marius Evers ,  Aparna Thyagarajan ,  Anthony Jarvis

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/3296

Abstract: A processor predicts a number of loop iterations associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component of an instruction pipeline of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer. In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit of the instruction pipeline.