公开(公告)号：US12153927B2

公开(公告)日：2024-11-26

申请号：US16889010

申请日：2020-06-01

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas Clouqueur ,  Marius Evers ,  Aparna Mandke ,  Steven R. Havlir ,  Robert Cohen ,  Anthony Jarvis

IPC: G06F9/38 ,  G06F9/48

Abstract: Merging branch target buffer entries includes maintaining, in a branch target buffer, an entry corresponding to first branch instruction, where the entry identifies a first branch target address for the first branch instruction and a second branch target address for a second branch instruction; and accessing, based on the first branch instruction, the entry.

公开(公告)号：US11507380B2

公开(公告)日：2022-11-22

申请号：US16116666

申请日：2018-08-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas Clouqueur

IPC: G06F9/38

Abstract: A processing system includes a processor with a branch predictor including one or more branch target buffer tables. The processor also includes a branch prediction pipeline including a throttle unit and an uncertainty accumulator. The processor assigns an uncertainty value for each of a plurality of branch predictions generated by the branch predictor and adds the uncertainty value for each of the plurality of branch predictions to an accumulated uncertainty counter associated with the uncertainty accumulator. The throttle unit of the branch prediction pipeline throttles operations of the branch prediction pipeline based on the accumulated uncertainty counter.

公开(公告)号：US11416253B2

公开(公告)日：2022-08-16

申请号：US16926339

申请日：2020-07-10

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Thomas Clouqueur ,  Anthony Jarvis

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor includes two or more branch target buffer (BTB) tables for branch prediction, each BTB table storing entries of a different target size or width or storing entries of a different branch type. Each BTB entry includes at least a tag and a target address. For certain branch types that only require a few target address bits, the respective BTB tables are narrower thereby allowing for more BTB entries in the processor separated into respective BTB tables by branch instruction type. An increased number of available BTB entries are stored in a same or a less space in the processor thereby increasing a speed of instruction processing. BTB tables can be defined that do not store any target address and rely on a decode unit to provide it. High value BTB entries have dedicated storage and are therefore less likely to be evicted than low value BTB entries.

公开(公告)号：US11216279B2

公开(公告)日：2022-01-04

申请号：US16200491

申请日：2018-11-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony Jarvis ,  Thomas Clouqueur

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: A processor includes a prediction engine coupled to a training engine. The prediction engine includes a loop exit predictor. The training engine includes a loop exit branch monitor coupled to a loop detector. Based on at least one of a plurality of call return levels, the loop detector of the processor takes a snapshot of a retired predicted block during a first retirement time, compares the snapshot to a subsequent retired predicted block at a second retirement time, and based on the comparison, identifies a loop and loop exit branches within the loop for use by the loop exit branch monitor and the loop exit predictor to determine whether to override a general purpose conditional prediction.