公开(公告)号：US09436567B2

公开(公告)日：2016-09-06

申请号：US13718944

申请日：2012-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Atchyuth K Gorti ,  Archana Somachudan

IPC: G06F11/00 ,  G06F11/27 ,  G11C29/16

CPC classification number: G06F11/27 ,  G11C29/16

Abstract: A scalable, reconfigurable Memory Built-In Self-Test (MBIST) architecture for a semiconductor device, such as a multiprocessor, having a Master and one or more Slave MBIST controllers is described. The MBIST architecture includes a plurality of MBISTDP interfaces connected in a ring with the Master MBIST controller. Each MBISTDP interface connects to at least one Slave controller for forwarding test information streamed to it from the Master MBIST controller over the ring. Test information includes test data, address, and MBIST test commands. Each MBISTDP interface forwards the information to the Slave controller attached thereto and to the next MBISTDP interface on the ring. Test result data is sent back to the Master MBIST controller from the MBISTDP interfaces over the ring.

Abstract translation: 描述了具有主和一个或多个从属MBIST控制器的半导体器件（例如多处理器）的可扩展的可重新配置的内存自测（MBIST）架构。 MBIST架构包括与主MBIST控制器以环形连接的多个MBISTDP接口。 每个MBISTDP接口连接至少一个从控制器，用于通过环从Master MBIST控制器转发测试信息。 测试信息包括测试数据，地址和MBIST测试命令。 每个MBISTDP接口将信息转发到连接到其上的从属控制器，并转发到环上的下一个MBISTDP接口。 测试结果数据从环上的MBISTDP接口发送回主MBIST控制器。

公开(公告)号：US09291676B2

公开(公告)日：2016-03-22

申请号：US13773501

申请日：2013-02-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Atchyuth K Gorti ,  Aditya Jagirdar ,  Bikash Kumar Agarwal ,  Eric Quinnell

IPC: G01R31/28 ,  G01R31/3185

CPC classification number: G01R31/318552 ,  G01R31/318594

Abstract: We report methods relating to scan warmup of integrated circuit devices. One such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit, wherein the scan clock second frequency is equal to a system clock frequency; and capturing the scan test response by a shift logic at the scan clock second frequency. We also report processors containing components configured to implement the method, and fabrication of such processors. The methods and their implementation may reduce di/dt events otherwise commonly occurring when testing logic elements of integrated circuit devices.

Abstract translation: 报告集成电路设备的扫描预热方法。 一种这样的方法可以包括以等于测试时钟频率的扫描时钟第一频率将扫描测试激励加载并从集成电路器件的第一组逻辑元件卸载扫描测试响应; 通过扫描预热单元将扫描时钟从第一频率调整到第二频率，其中扫描时钟第二频率等于系统时钟频率; 并且以扫描时钟第二频率通过移位逻辑捕获扫描测试响应。 我们还会报告包含配置为实现该方法的组件以及这些处理器的制造的处理器。 这些方法及其实现可以减少在测试集成电路器件的逻辑元件时通常发生的di / dt事件。