公开(公告)号：US20210165739A1

公开(公告)日：2021-06-03

申请号：US16700671

申请日：2019-12-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sriram SRINIVASAN ,  John KELLEY ,  Matthew SCHOENWALD

IPC: G06F12/084

Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.

公开(公告)号：US20220237120A1

公开(公告)日：2022-07-28

申请号：US17666950

申请日：2022-02-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sriram SRINAVASAN ,  John KELLEY ,  Mathew SCHOENWALD

IPC: G06F12/084

Abstract: A processing system includes a plurality of compute units, with each compute unit having an associated first cache of a plurality of first caches, and a second cache shared by the plurality of compute units. The second cache operates to manage transfers of caches between the first caches of the plurality of first caches such that when multiple candidate first caches contain a valid copy of a requested cacheline, the second cache selects the candidate first cache having the shortest total path from the second cache to the candidate first cache and from the candidate first cache to the compute unit issuing a request for the requested cacheline.

公开(公告)号：US20220121579A1

公开(公告)日：2022-04-21

申请号：US17553044

申请日：2021-12-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul MOYER ,  John KELLEY

IPC: G06F12/12

Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.

公开(公告)号：US20210133114A1

公开(公告)日：2021-05-06

申请号：US16669973

申请日：2019-10-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul MOYER ,  John KELLEY

IPC: G06F12/12

Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.