公开(公告)号：US20190163656A1

公开(公告)日：2019-05-30

申请号：US15826065

申请日：2017-11-29

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Eric Christopher MORTON ,  Elizabeth COOPER ,  William L. WALKER ,  Douglas Benson HUNT ,  Richard Martin BORN ,  Richard H. Lee ,  Paul C. MIRANDA ,  Philip NG ,  Paul MOYER

IPC: G06F13/28 ,  G06F12/0891 ,  G06F12/0862 ,  G06F12/0815 ,  G06F12/0893

CPC classification number: G06F13/28 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/0893

Abstract: A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.

公开(公告)号：US20230205700A1

公开(公告)日：2023-06-29

申请号：US17564141

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Tarun NAKRA ,  Akhil ARUNKUMAR ,  Paul MOYER ,  Jay FLEISCHMAN

IPC: G06F12/0862 ,  G06F12/0811 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F9/3842 ,  G06F9/30047 ,  G06F2212/1021

Abstract: In response to generating one or more speculative prefetch requests for a last-level cache, a processor determines prefetch analytics for the generated speculative prefetch requests and compares the determined prefetch analytics of the speculative prefetch requests to selection thresholds. In response to a speculative prefetch request meeting or exceeding a selection threshold, the processor selects the speculative prefetch request for issuance to a memory-side cache controller. When one or more system conditions meet one or more condition thresholds, the processor issues the selected speculative prefetch request to the memory-side cache controller. The memory-side cache controller then retrieves the data indicated in the selected speculative prefetch request from a memory and stores it in a memory-side cache in the data fabric coupled to the last-level cache.

公开(公告)号：US20190121748A1

公开(公告)日：2019-04-25

申请号：US15790743

申请日：2017-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul MOYER

IPC: G06F12/128 ,  G06F12/0811 ,  G06F12/0895

Abstract: A system includes one or more processor cores and a cache hierarchy. The cache hierarchy includes a first-level cache, a second-level cache, and a third-level cache. The cache hierarchy further includes cache hierarchy control logic configured to implement a caching policy in which each cacheline cached in the first-level cache has a copy of the cacheline cached in at least one of the second-level cache and the third-level cache. The caching policy further provides that an eviction of a cacheline from the second-level cache does not trigger an eviction of a copy of that cacheline from the first-level cache, and that an eviction of a cacheline from the third-level cache triggers the cache hierarchy control logic to evict a copy of that cacheline from the first-level cache when the cacheline is not present in the second-level cache.

公开(公告)号：US20190121747A1

公开(公告)日：2019-04-25

申请号：US15790616

申请日：2017-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul MOYER

IPC: G06F12/128 ,  G06F12/122 ,  G06F12/0811 ,  G06F12/0875

Abstract: A cache controller determines replacement priority for cache lines at a cache based on data stored at non-cache buffers. In response to determining that a cache line at the cache is to be replaced, the cache controller identifies a set of candidate cache lines for replacement. The cache controller probes the non-cache buffers to identify any entries that are assigned to the same memory address as a candidate cache line and adjusts the replacement priorities for the candidate cache lines based on the probe responses. The cache controller deprioritizes for replacement cache lines associated with entries of the non-cache buffers.

公开(公告)号：US20220121579A1

公开(公告)日：2022-04-21

申请号：US17553044

申请日：2021-12-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul MOYER ,  John KELLEY

IPC: G06F12/12

Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.

公开(公告)号：US20210133114A1

公开(公告)日：2021-05-06

申请号：US16669973

申请日：2019-10-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul MOYER ,  John KELLEY

IPC: G06F12/12

Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.

公开(公告)号：US20200242049A1

公开(公告)日：2020-07-30

申请号：US16256634

申请日：2019-01-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H. LOH ,  Paul MOYER

IPC: G06F12/126 ,  G06F12/1027 ,  G06F12/0808 ,  G06F12/0871

Abstract: A processing system adjusts a cache replacement priority of cache lines at a cache based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and evicts the cache lines or adjusts the cache replacement priority of the cache lines so that their eviction from the cache will be accelerated.

公开(公告)号：US20200081849A1

公开(公告)日：2020-03-12

申请号：US16681617

申请日：2019-11-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul MOYER

IPC: G06F12/123 ,  G06F12/0862

Abstract: A cache controller applies an aging policy to a portion of a cache based on access metrics for different test regions of the cache, whereby each test region implements a different aging policy. The aging policy for each region establishes an initial age value for each entry of the cache, and a particular aging policy can set the age for a given entry based on whether the entry was placed in the cache in response to a demand request from a processor core or in response to a prefetch request. The cache controller can use the age value of each entry as a criterion in its cache replacement policy.