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公开(公告)号：US20240320777A1
公开(公告)日：2024-09-26
申请号：US18434319
申请日：2024-02-06
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Christopher J. BRENNAN , Nishank PATHAK
Abstract: A graphics pipeline includes a first shader that generates first wave groups, a shader processor input (SPI) that launches the first wave groups for execution by shaders, and a scan converter that generates second waves for execution on the shaders based on results of processing the first wave groups the one or more shaders. The first wave groups are selectively throttled based on a comparison of in-flight first wave groups and second waves pending execution on the at least one second shader. A cache holds information that is written to the cache in response to the first wave groups finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first wave groups are selectively throttled by comparing how many first wave groups are in-flight and how many read requests to the cache are pending.
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公开(公告)号：US20220318944A1
公开(公告)日：2022-10-06
申请号：US17217050
申请日：2021-03-30
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Christopher J. BRENNAN , Nishank PATHAK
Abstract: A graphics pipeline includes a first shader that generates first wave groups, a shader processor input (SPI) that launches the first wave groups for execution by shaders, and a scan converter that generates second waves for execution on the shaders based on results of processing the first wave groups the one or more shaders. The first wave groups are selectively throttled based on a comparison of in-flight first wave groups and second waves pending execution on the at least one second shader. A cache holds information that is written to the cache in response to the first wave groups finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first wave groups are selectively throttled by comparing how many first wave groups are in-flight and how many read requests to the cache are pending.
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公开(公告)号：US20210150658A1
公开(公告)日：2021-05-20
申请号：US16683868
申请日：2019-11-14
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mangesh P. NIJASURE , Tad LITWILLER , Todd MARTIN , Nishank PATHAK
Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that at least the threshold percentage of the tessellation factors for the thread group are the same (or, additionally, that at least the threshold percentage of the tessellation factors have a value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline), the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to the graphics memory, thus reducing bandwidth and increasing efficiency of the graphics pipeline.
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Patent Agency Ranking
公开(公告)号：US20220188963A1
公开(公告)日：2022-06-16
申请号：US17123978
申请日：2020-12-16
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Nishank PATHAK , Randy Wayne RAMSEY , Tad LITWILLER , Rex Eldon MCCRARY
Abstract: A processing system includes a graphics pipeline that executes a first shader of a first type and a second shader of a second type. In some cases, the first shader is a geometry shader and the second shader is a pixel shader. The processing system also includes buffers that hold primitives generated by the first shader and provide the primitives to the second shader. The processing system also includes a primitive hub that monitors fullness of the buffers. Launching of waves from the first shader is throttled based on the fullness of the buffers. A shader processor input (SPI) selectively throttles the waves launched by the geometry shader based on a signal from the primitive hub indicating the fullness, an indication of relative resource usage of geometry waves and pixel waves in the graphics pipeline, or an indication of lifetimes of the geometry waves.
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公开(公告)号：US20210183004A1
公开(公告)日：2021-06-17
申请号：US16713472
申请日：2019-12-13
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Todd MARTIN , Tad LITWILLER , Nishank PATHAK , Mangesh P. NIJASURE
IPC: G06T1/20 , H04L12/861 , H04L12/863
Abstract: A graphics processing unit (GPU) includes a packet management component that automatically aggregates data from input packets. In response to determining that a received first input packet does not indicate a send condition, and in response to determining that a generated output packet would be smaller than an output size threshold, the packet management component aggregates data corresponding to the first input packet with data corresponding to a second input packet stored at a packet buffer. In response to determining that a received third input packet indicates a send condition, the packet management component sends the aggregated data to a compute unit in an output packet and performs an operation indicated by the send condition.
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公开(公告)号：US20230169728A1
公开(公告)日：2023-06-01
申请号：US17974199
申请日：2022-10-26
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Nishank PATHAK
CPC classification number: G06T17/20 , G06T15/005
Abstract: A processing system includes hull shader circuitry that launches thread groups including one or more primitives. The hull shader circuitry also generates tessellation factors that indicate subdivisions of the primitives. The processing system also includes throttling circuitry that estimates a primitive launch time interval for the domain shader based on the tessellation factors and selectively throttles launching of the thread groups from the hull shader circuitry based on the primitive launch time interval of the domain shader and a hull shader latency. In some cases, the throttling circuitry includes a first counter that is incremented in response to launching a thread group from the buffer and a second counter that modifies the first counter based on a measured latency of the domain shader.
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公开(公告)号：US20220189112A1
公开(公告)日：2022-06-16
申请号：US17121965
申请日：2020-12-15
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Nishank PATHAK
Abstract: A processing system includes hull shader circuitry that launches thread groups including one or more primitives. The hull shader circuitry also generates tessellation factors that indicate subdivisions of the primitives. The processing system also includes throttling circuitry that estimates a primitive launch time interval for the domain shader based on the tessellation factors and selectively throttles launching of the thread groups from the hull shader circuitry based on the primitive launch time interval of the domain shader and a hull shader latency. In some cases, the throttling circuitry includes a first counter that is incremented in response to launching a thread group from the buffer and a second counter that modifies the first counter based on a measured latency of the domain shader.
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公开(公告)号：US20210374898A1
公开(公告)日：2021-12-02
申请号：US17318523
申请日：2021-05-12
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mangesh P. NIJASURE , Tad LITWILLER , Todd MARTIN , Nishank PATHAK
Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that at least the threshold percentage of the tessellation factors for the thread group are the same (or, additionally, that at least the threshold percentage of the tessellation factors have a value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline), the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to the graphics memory, thus reducing bandwidth and increasing efficiency of the graphics pipeline.
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