公开(公告)号：US20230004400A1

公开(公告)日：2023-01-05

申请号：US17943265

申请日：2022-09-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： JYOTI RAHEJA ,  HIDEKI KANAYAMA ,  GUHAN KRISHNAN ,  RUIHUA PENG

IPC: G06F9/4401 ,  G06F1/3234 ,  G06F12/0804 ,  G06F1/3287

Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.