公开(公告)号：US20190005604A1

公开(公告)日：2019-01-03

申请号：US15639980

申请日：2017-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Anirudh R. ACHARYA ,  Michael MANTOR ,  Vineet GOEL ,  Swapnil SAKHARSHETE

IPC: G06T1/20 ,  G06T15/00 ,  G06T17/10

Abstract: A stage of a graphics pipeline in a graphics processing unit (GPU) detects an interrupt concurrently with the stage processing primitives in a first bin that represents a first portion of a first frame generated by a first application. The stage forwards a completed portion of the primitives to a subsequent stage of the graphics pipeline in response to the interrupt. The stage diverts a second bin that represents a second portion of the first frame from the stage to a memory in response to the interrupt. The stage processes primitives in a third bin that represents a portion of a second frame generated by a second application subsequent to diverting the second bin to the memory. The stage can then retrieve the second bin from the memory in response to the stage completing processing of the primitives in the third bin for additional processing.

公开(公告)号：US20190164328A1

公开(公告)日：2019-05-30

申请号：US16238727

申请日：2019-01-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anirudh R. ACHARYA ,  Swapnil SAKHARSHETE ,  Michael MANTOR ,  Mangesh P. NIJASURE ,  Todd MARTIN ,  Vineet GOEL

IPC: G06T15/00 ,  G06T1/20 ,  G06F9/48 ,  G06T15/80 ,  G06F9/50

Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.