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公开(公告)号:US20240330214A1
公开(公告)日:2024-10-03
申请号:US18191207
申请日:2023-03-28
发明人: Lianji Cheng , Xiao Han , Qing Li
IPC分类号: G06F13/24
CPC分类号: G06F13/24
摘要: An apparatus includes logic circuitry, such as an interrupt controller, that serially arbitrates among a plurality of incoming interrupt requests for a target device and produces a selected incoming interrupt request. The logic generates a message signaled interrupt (MSI) message for the target device based on the selected incoming interrupt request using a plurality of linked lookup tables, such as a hierarchy of LUTs that include data used to generate the MSI message. Associated methods are also presented.