公开(公告)号：US20230057398A1

公开(公告)日：2023-02-23

申请号：US17790390

申请日：2019-12-31

Applicant: AGENCY FOR SCIENCE TECHNOLOGY AND RESEARCH ,  SEMBCORP INDUSTRIES LTD.

Inventor： Jianzhong HAO ,  Wenyu JIANG ,  Yixin WANG ,  Aayush MADAN ,  Shili XIANG ,  Jun Long LIM ,  Ouyang LIU ,  Yongwei ZHU ,  Kai WU ,  Jiliang Eugene PHUA ,  Rebecca Yen-Ni WONG ,  MURALIDHARAN S/O PARAMSOTHY ,  Hui DONG ,  Chuen Yuen Henry WONG ,  Wen CHEN ,  Haiyan SHU

IPC: G01B11/06 ,  G01D5/353 ,  F17C13/02

Abstract: The present disclosure relates to at least one method for ascertaining at least one attribute of pressure vessel wall. A method comprises: while a pressure vessel, which comprises a wall having an outer surface and an inner surface, is operating: ascertaining a current wavelength shift of a first fiber Bragg grating (FBG) sensor disposed at a first outer surface location on the pressure vessel; and ascertaining a current thickness of the wall at the first outer surface location by: computing a vector based on a time series of the current wavelength shift, or a derivative of the time series, or a derivative of the current wavelength shift; providing the vector to a predetermined regression model; and using the regression model, ascertaining the current thickness of the wall.

公开(公告)号：US20170169075A1

公开(公告)日：2017-06-15

申请号：US15121991

申请日：2015-03-02

Applicant: Agency for Science, Technology and Research

Inventor： Wenyu JIANG ,  Rongshan YU ,  Xiaoming BAO ,  Susanto RAHARDJA

IPC: G06F17/30 ,  G11C16/26 ,  G11C16/04 ,  G06F3/06

CPC classification number: G06F16/24569 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0679 ,  G11C13/0002 ,  G11C15/046 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

Abstract: According to various embodiments, a testing apparatus may be provided. The testing apparatus may include: a cell pair comprising two l-bit memory cells configured to represent a stored pattern of l-bit; and a converter configured to convert a query pattern of l-bit into a pair of voltages defined such that when applied to gates of the cell pair, the voltages make the cell pair into high resistance mode when the query pattern matches the stored pattern and into low resistance mode when the query pattern does not match the stored pattern.

公开(公告)号：US20240296311A1

公开(公告)日：2024-09-05

申请号：US18548870

申请日：2023-03-03

Applicant: Agency for Science, Technology and Research

Inventor： Vishnu PARAMASIVAM ,  Wenyu JIANG ,  Anh Tuan DO ,  Ming Ming WONG ,  Aarthy MANI ,  Sumit Bam SHRESTHA

IPC: G06N3/045 ,  G06N3/091

CPC classification number: G06N3/045 ,  G06N3/091

Abstract: There is provided a neural network processor system including: a neural processing unit including a plurality of neural processing cores; a router network including a plurality of routers communicatively coupled to the plurality of neural processing cores, respectively; and a host processing unit communicatively coupled to the neural processing unit based on the router network and configured to coordinate the neural processing unit for performing neural network computations. Each neural processing core includes: a control register block configured to receive and store partial sum configuration information from the host processing unit; and a partial sum interface communicatively coupled to the control register block and configured to transmit a first partial sum neural packet generated by the neural processing core to a first another neural processing core of the plurality of neural processing cores and/or receive a second partial sum neural packet generated by a second another neural processing core of the plurality of neural processing cores, based on the partial sum configuration information stored in the neural processing core. Furthermore, a first set of neural processing cores of the plurality of neural processing cores are combinable based on the partial sum configuration information respectively stored therein to form a first neurosynaptic column chain. There is also provided a corresponding method of operating and a corresponding method of forming the neural network processor system.

公开(公告)号：US20230351195A1

公开(公告)日：2023-11-02

申请号：US18042718

申请日：2020-08-31

Applicant: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH

Inventor： Ming Ming WONG ,  Sumit Bam SHRESTHA ,  Vishnu PARAMASIVAM ,  Aarthy MANI ,  Wenyu JIANG ,  Anh Tuan DO

IPC: G06N3/088 ,  G06N3/049

CPC classification number: G06N3/088 ,  G06N3/049

Abstract: There is provided a neurosynaptic processing core with spike time dependent plasticity (STDP) learning for a spiking neural network, including: a spiking neuron block including a pre-synaptic block and a post-synaptic block; a synapse block communicatively coupled to the spiking neuron block; a STDP learning block communicatively coupled to the spiking neuron block and the synapse block, the STDP learning block including a pre-synaptic event accumulator including a pre-synaptic spike event memory block and a pre-synaptic spike parameter modifier; a post-synaptic event accumulator including a post-synaptic spike event memory block and a post-synaptic spike parameter modifier, a weight change accumulator, and a weight change parameter modifier; a learning error modulator; and a synaptic weight modifier configured to modify a synaptic weight parameter based on a weight change parameter and a learning error corresponding to the synaptic weight parameter. There is also provided a corresponding method of operating and a corresponding method of forming the neurosynaptic processing core.