公开(公告)号：US11721665B2

公开(公告)日：2023-08-08

申请号：US17750118

申请日：2022-05-20

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Yan Xun Xue ,  Madhur Bobde ,  Long-Ching Wang ,  Bo Chen

IPC: H01L21/32 ,  H01L23/00 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L24/97 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/32 ,  H01L2221/68327 ,  H01L2221/68368 ,  H01L2224/32245 ,  H01L2224/95001

Abstract: A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.

公开(公告)号：US20220278076A1

公开(公告)日：2022-09-01

申请号：US17750118

申请日：2022-05-20

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Yan Xun Xue ,  Madhur Bobde ,  Long-Ching Wang ,  Bo Chen

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78

Abstract: A wafer level chip scale semiconductor package comprises a device semiconductor layer, a backside metallization layer, a film laminate layer, and a metal layer. The device semiconductor layer comprises a plurality of metal electrodes disposed on a front surface of the device semiconductor. Each side surface of the backside metallization layer is coplanar with a corresponding side surface of the device semiconductor layer. Each side surface of the metal layer is coplanar with a corresponding side surface of the film laminate layer. A surface area of a back surface of the backside metallization layer is smaller than a surface area of a front surface of the metal layer.

公开(公告)号：US11784141B2

公开(公告)日：2023-10-10

申请号：US17960700

申请日：2022-10-05

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Jun Lu ,  Long-Ching Wang ,  Madhur Bobde ,  Bo Chen ,  Shuhua Zhou

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/15

CPC classification number: H01L23/562 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/15 ,  H01L23/3114 ,  H01L2221/68327

Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulaton process so as to form a plurality of semiconductor packages.

公开(公告)号：US20210125940A1

公开(公告)日：2021-04-29

申请号：US17137893

申请日：2020-12-30

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Jun Lu ,  Long-Ching Wang ,  Madhur Bobde ,  Bo Chen ,  Shuhua Zhou

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/15 ,  H01L21/78 ,  H01L21/683

Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulation process so as to form a plurality of semiconductor packages.

公开(公告)号：US20230021687A1

公开(公告)日：2023-01-26

申请号：US17960700

申请日：2022-10-05

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Jun Lu ,  Long-Ching Wang ,  Madhur Bobde ,  Bo Chen ,  Shuhua Zhou

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/683 ,  H01L23/15

Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulaton process so as to form a plurality of semiconductor packages.

公开(公告)号：US11495548B2

公开(公告)日：2022-11-08

申请号：US17137893

申请日：2020-12-30

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Jun Lu ,  Long-Ching Wang ,  Madhur Bobde ,  Bo Chen ,  Shuhua Zhou

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L23/15

Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulation process so as to form a plurality of semiconductor packages.

公开(公告)号：US11430762B2

公开(公告)日：2022-08-30

申请号：US17137811

申请日：2020-12-30

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Yan Xun Xue ,  Madhur Bobde ,  Long-Ching Wang ,  Bo Chen

IPC: H01L21/683 ,  H01L23/00 ,  H01L21/78

Abstract: A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.

公开(公告)号：US20220208724A1

公开(公告)日：2022-06-30

申请号：US17137811

申请日：2020-12-30

Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP

Inventor： Yan Xun Xue ,  Madhur Bobde ,  Long-Ching Wang ,  Bo Chen

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78

Abstract: A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.