Huffman code generation
    1.
    发明授权

    公开(公告)号:US09698819B1

    公开(公告)日:2017-07-04

    申请号:US15390304

    申请日:2016-12-23

    CPC classification number: H03M7/40 H03M7/30 H03M7/405 H03M7/42 H03M7/6076

    Abstract: A method for generating Huffman codewords to encode a dataset includes selecting a Huffman tree type from a plurality of different Huffman tree types. Each of the Huffman tree types specifies a different range of codeword length in a Huffman tree. A Huffman tree of the selected type is produced by: determining a number of nodes available to be allocated as leaves in each level of the Huffman tree accounting for allocation of leaves in each level of the Huffman tree; allocating nodes to be leaves such that the number of nodes allocated in a given level of the Huffman tree is constrained to be no more than the number of nodes available to be allocated in the given level; and assigning the leaves to symbols of the dataset based an assignment strategy selected from a plurality of assignment strategies to produce symbol codeword information.

    Checksum circuit
    2.
    发明授权

    公开(公告)号:US09983851B1

    公开(公告)日:2018-05-29

    申请号:US15274844

    申请日:2016-09-23

    CPC classification number: G06F7/727

    Abstract: A hardware circuit computes a checksum using a technique such as the Adler-32 checksum algorithm. The hardware circuit may include one or more serially-connected chains of adders followed by a modulus circuit. The modulus circuit produces a modulus value in N, where N is not an integer power of 2. In some examples, N is 65,521. In some examples, the modulus circuit may produce a modulus value modulo 216 and then correct that value to modulo N. In other examples, the modulus circuit may include selection logic that selects an appropriate integer multiple of 65,521 to determine the modulo 65,521 result directly.

    Extending cryptographic-key lifespan in network encryption protocols

    公开(公告)号:US10708246B1

    公开(公告)日:2020-07-07

    申请号:US15836292

    申请日:2017-12-08

    Abstract: An apparatus and a corresponding method. The apparatus includes an injection module operable to maintain packet sequence numbers for a group of network devices, receive a first packet and a second packet that is sent from the apparatus after the first packet and destined for a different device in the group than the first packet, and update the packets with different packet sequence numbers. The packet sequence number for the second packet is generated using the packet sequence number for the first packet. The apparatus further includes an encryption module operable to determine an initialization vector for each packet sequence number and apply an encryption algorithm to each packet. Each packet is encrypted using a corresponding initialization vector and an encryption key as inputs to the encryption algorithm.

    Speculative data decompression
    4.
    发明授权

    公开(公告)号:US10020819B1

    公开(公告)日:2018-07-10

    申请号:US15718669

    申请日:2017-09-28

    Abstract: A computing system includes a network interface, a processor, and a decompression circuit. In response to a compression request from the processor the decompression circuit compresses data to produce compressed data and transmits the compressed data through the network interface. In response to a decompression request from the processor for compressed data the decompression circuit retrieves the requested compressed data, speculatively detects codewords in each of a plurality of overlapping bit windows within the compressed data, selects valid codewords from some, but not all of the overlapping bit windows, decodes the selected valid codewords to generate decompressed data, and provides the decompressed data to the processor.

    Configurable compression circuit
    5.
    发明授权

    公开(公告)号:US10432216B1

    公开(公告)日:2019-10-01

    申请号:US15614161

    申请日:2017-06-05

    Abstract: A compression circuit includes a buffer, a selection circuit, a compare circuit, and a control circuit. The buffer stores uncompressed data. The selection circuit generates a read pointer value to the buffer. The control circuit contains a programmable configuration register. The configuration register stores a depth value for reading uncompressed data from the history buffer. The control circuit generates control signals to the selection circuit to cause the selection circuit to iteratively increment the read pointer value from an initial value to a second value that corresponds to the depth value. Responsive to the second value corresponding to the depth value, the control circuit resets the read pointer value to the initial value. The compare circuit compares input symbols from a data source to uncompressed data from the buffer history to thereby generate output compressed data.

    Performing parallel deflate compression

    公开(公告)号:US10284226B1

    公开(公告)日:2019-05-07

    申请号:US16029805

    申请日:2018-07-09

    Abstract: A computing system includes a network interface, a processor, and a decompression circuit. In response to a compression request from the processor the decompression circuit compresses data to produce compressed data and transmits the compressed data through the network interface. In response to a decompression request from the processor for compressed data the decompression circuit retrieves the requested compressed data, speculatively detects codewords in each of a plurality of overlapping bit windows within the compressed data, selects valid codewords from some, but not all of the overlapping bit windows, decodes the selected valid codewords to generate decompressed data, and provides the decompressed data to the processor.

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