公开(公告)号：US09983851B1

公开(公告)日：2018-05-29

申请号：US15274844

申请日：2016-09-23

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Michael Baranchik ,  Svetlana Kantorovych ,  Ori Weber

IPC: G06F7/72

CPC classification number: G06F7/727

Abstract: A hardware circuit computes a checksum using a technique such as the Adler-32 checksum algorithm. The hardware circuit may include one or more serially-connected chains of adders followed by a modulus circuit. The modulus circuit produces a modulus value in N, where N is not an integer power of 2. In some examples, N is 65,521. In some examples, the modulus circuit may produce a modulus value modulo 216 and then correct that value to modulo N. In other examples, the modulus circuit may include selection logic that selects an appropriate integer multiple of 65,521 to determine the modulo 65,521 result directly.

公开(公告)号：US10168909B1

公开(公告)日：2019-01-01

申请号：US15084013

申请日：2016-03-29

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Svetlana Kantorovych ,  Georgy Machulsky ,  Ori Weber ,  Nafea Bshara

IPC: G06F11/34 ,  G06F3/06

Abstract: Described herein are techniques for providing data compression and decompression within the bounds of hardware constraints. In some embodiments, the disclosure provides that a processing entity may load a portion of a data stream into a memory buffer. In some embodiments, the size of the portion of data loaded into the memory buffer may be determined based on a capacity of the memory buffer. The processing entity may determine whether the portion of data loaded into the memory buffer includes matching data segments. Upon determining that the portion of data does not include matching data segments, the processing entity may generate a sequence that includes uncompressed data and an indication that the sequence contains no matching data segments.

公开(公告)号：US10432216B1

公开(公告)日：2019-10-01

申请号：US15614161

申请日：2017-06-05

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Svetlana Kantorovych ,  Ori Weber ,  Michael Baranchik

IPC: H03M7/30 ,  H03K19/173 ,  G06F16/25

Abstract: A compression circuit includes a buffer, a selection circuit, a compare circuit, and a control circuit. The buffer stores uncompressed data. The selection circuit generates a read pointer value to the buffer. The control circuit contains a programmable configuration register. The configuration register stores a depth value for reading uncompressed data from the history buffer. The control circuit generates control signals to the selection circuit to cause the selection circuit to iteratively increment the read pointer value from an initial value to a second value that corresponds to the depth value. Responsive to the second value corresponding to the depth value, the control circuit resets the read pointer value to the initial value. The compare circuit compares input symbols from a data source to uncompressed data from the buffer history to thereby generate output compressed data.

公开(公告)号：US11182103B1

公开(公告)日：2021-11-23

申请号：US16261198

申请日：2019-01-29

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Adi Habusha ,  Uri Leder ,  Svetlana Kantorovych

IPC: G06F3/06 ,  G06F12/0806 ,  G06F12/0875 ,  G06F12/0873

Abstract: A dedicated input/output (I/O) cache can be used for I/O-to-processor communications. Data received from an I/O device can be written to the I/O cache and also written to a device memory that is accessible to the processor. The processor can then access the data in the fast, dedicated I/O cache if available. Otherwise, the processor can read the data from the memory into a conventional processor cache for processing. Writes to the cache can be full or partial, with partial writes utilizing padding in some embodiments. The data can be written sequentially in a circular manner. Data processed by the processor can be invalidated, and invalidated data can be overwritten on a subsequent write. Phase bits can also be used to indicate the pass during which various writes were performed.