公开(公告)号：US20160182078A1

公开(公告)日：2016-06-23

申请号：US14949423

申请日：2015-11-23

Applicant: ANALOG DEVICES, INC.

Inventor： JUNHUA SHEN ,  Mark D. Maddox ,  Ronald Alan Kapusta

IPC: H03M1/46 ,  H03M1/00

CPC classification number: H03M1/468 ,  H03M1/002 ,  H03M1/08 ,  H03M1/462

Abstract: A successive approximation register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal independent (can be easily measured and corrected/calibrated).

Abstract translation: 逐次逼近寄存器模拟 - 数字转换器（SAR ADC）通常包括用于实现将模拟输入逐位转换为数字输出的位测试的电路。 用于比特测试的电路通常是加权（例如，二进制加权），并且这些比特权重并不总是理想的。 校准算法可校准或校正非理想比特权重，并且通常将这些比特权重优先于信号无关，以便可以容易地测量和校准/校正比特权重。 本文公开的实施例涉及SAR ADC的独特电​​路设计，其中每个位电容器或一对位电容器（在差分设计中）具有相应的专用片上参考电容器。 由于片上参考电容（提供快速参考建立时间），所得ADC的速度很快，而与SAR ADC的非理想位权重有关的错误与信号无关（可以轻松测量和校正/校准） 。