公开(公告)号：US09491495B2

公开(公告)日：2016-11-08

申请号：US14598299

申请日：2015-01-16

Applicant: ANALOG DEVICES GLOBAL

Inventor： Chris W. Bohm ,  Narsimh Dilip Kamath

IPC: H04L25/49 ,  H04N21/236 ,  H04N21/414 ,  B60R11/04 ,  H04H20/62 ,  H04N21/4223 ,  H04N21/2365 ,  H04N21/234 ,  H04L25/493 ,  H04L1/00

CPC classification number: H04N21/23602 ,  B60R11/04 ,  G06F13/38 ,  G06F13/4291 ,  H04H20/62 ,  H04L1/0057 ,  H04L25/4904 ,  H04L25/493 ,  H04N7/18 ,  H04N7/181 ,  H04N21/23406 ,  H04N21/2365 ,  H04N21/41422 ,  H04N21/4223 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system for receiving at least two data streams and providing a single input data stream to a MIPI's CSI Tx is disclosed. The two received data streams are written into respective data buffers. The system includes a control logic configured to control reading of data stored in the buffers to a multiplexer, the read-side clock being a multiple of a frequency of a fixed frequency clock. The control logic is further configured to control the multiplexer to combine data read from each buffer that corresponds to a complete unit of data into a separate portion and multiplex the separate portions into the input data stream. In this manner, two data streams may be transmitted using a single CSI Tx. When the two data streams are received by the system from an APIX interface, the system provides a bridge between the APIX interface and MIPI's CSI Tx.

Abstract translation: 公开了一种用于接收至少两个数据流并向MIPI的CSI Tx提供单个输入数据流的系统。 两个接收的数据流被写入相应的数据缓冲器。 该系统包括控制逻辑，其被配置为控制将存储在缓冲器中的数据读取到多路复用器，读侧时钟是固定频率时钟频率的倍数。 控制逻辑还被配置为控制多路复用器将从对应于完整数据单元的每个缓冲器读取的数据组合成单独的部分，并将分离的部分复用到输入数据流中。 以这种方式，可以使用单个CSI Tx发送两个数据流。 当系统从APIX接口接收到两个数据流时，系统提供了APIX接口和MIPI的CSI Tx之间的桥梁。

公开(公告)号：US10320407B1

公开(公告)日：2019-06-11

申请号：US15890086

申请日：2018-02-06

Applicant: Analog Devices Global Unlimited Company

Inventor： Narsimh Dilip Kamath

IPC: H03M1/00 ,  H03M1/06 ,  G06F3/05 ,  H03M1/14

Abstract: A system having two or more sensing nodes coupled to a control node using a serial communication channel having separate transmit and receive circuits, where each sensing node includes an ADC circuit and a microcontroller, operation of the ADC circuit in each sensing node is concurrently synchronized by the control node using the transmit circuit (e.g., with respect to the control node) of the serial communication channel. The control node can synchronize operation of two or more ADC circuits in separate sensing nodes without using shared clocks or other control signals.

公开(公告)号：US20160212456A1

公开(公告)日：2016-07-21

申请号：US14598299

申请日：2015-01-16

Applicant: ANALOG DEVICES GLOBAL

Inventor： Chris W. Bohm ,  Narsimh Dilip Kamath

IPC: H04N21/236 ,  B60R11/04 ,  H04N21/234 ,  H04N21/4223 ,  H04N21/2365 ,  H04N21/414 ,  H04H20/62

CPC classification number: H04N21/23602 ,  B60R11/04 ,  G06F13/38 ,  G06F13/4291 ,  H04H20/62 ,  H04L1/0057 ,  H04L25/4904 ,  H04L25/493 ,  H04N7/18 ,  H04N7/181 ,  H04N21/23406 ,  H04N21/2365 ,  H04N21/41422 ,  H04N21/4223 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system for receiving at least two data streams and providing a single input data stream to a MIPI's CSI Tx is disclosed. The two received data streams are written into respective data buffers. The system includes a control logic configured to control reading of data stored in the buffers to a multiplexer, the read-side clock being a multiple of a frequency of a fixed frequency clock. The control logic is further configured to control the multiplexer to combine data read from each buffer that corresponds to a complete unit of data into a separate portion and multiplex the separate portions into the input data stream. In this manner, two data streams may be transmitted using a single CSI Tx. When the two data streams are received by the system from an APIX interface, the system provides a bridge between the APIX interface and MIPI's CSI Tx.

Abstract translation: 公开了一种用于接收至少两个数据流并向MIPI的CSI Tx提供单个输入数据流的系统。 两个接收的数据流被写入相应的数据缓冲器。 该系统包括控制逻辑，其被配置为控制将存储在缓冲器中的数据读取到多路复用器，读侧时钟是固定频率时钟频率的倍数。 控制逻辑还被配置为控制多路复用器将从与完整数据单元对应的每个缓冲器读取的数据组合成单独的部分，并将分离的部分复用到输入数据流中。 以这种方式，可以使用单个CSI Tx发送两个数据流。 当系统从APIX接口接收到两个数据流时，系统提供了APIX接口和MIPI的CSI Tx之间的桥梁。