公开(公告)号：US20140115302A1

公开(公告)日：2014-04-24

申请号：US13963793

申请日：2013-08-09

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Boris Lemer ,  Kaushal Sanghai ,  Michael G. Perkins ,  John L. Redford ,  Michael S. Allen

IPC: G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3887

Abstract: According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Abstract translation: 根据示例性实施例，诸如数字信号处理器（DSP）的处理器被提供有用作谓词计数器的寄存器。 谓词计数器可以包括两个有用的值，并且除了用作执行指令的条件之外，还可以跟踪循环或条件分支内的嵌套级别。 在某些情况下，谓词计数器可以被配置为在单指令，多数据（SIMD）模式或SIMD-在寄存器（SWAR）模式下操作。