公开(公告)号：US09342306B2

公开(公告)日：2016-05-17

申请号：US13963793

申请日：2013-08-09

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Boris Lerner ,  Kaushal Sanghai ,  Michael G. Perkins ,  John L. Redford ,  Michael S. Allen

IPC: G06F9/44 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30072 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3887

Abstract: According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Abstract translation: 根据示例性实施例，诸如数字信号处理器（DSP）的处理器被提供有用作谓词计数器的寄存器。 谓词计数器可以包括两个有用的值，并且除了用作执行指令的条件之外，还可以跟踪循环或条件分支中的嵌套级别。 在某些情况下，谓词计数器可以被配置为在单指令，多数据（SIMD）模式或SIMD-在寄存器（SWAR）模式下操作。

公开(公告)号：US20140115195A1

公开(公告)日：2014-04-24

申请号：US14040367

申请日：2013-09-27

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Michael S. Allen ,  John L. Redford

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

Abstract translation: 根据一个示例实施例，公开了直接存储器存取（DMA）引擎和缓冲器。 向量缓冲器可以是可显式可编程的，并且可以包括用于重新排序非单位步幅矢量数据的高级逻辑。 示例MEMCPY指令可以向DMA缓冲器提供访问请求，其可以异步地服务请求。 按位保护设置在使用中的内存中，并在读取每个位时清零。

公开(公告)号：US20160034399A1

公开(公告)日：2016-02-04

申请号：US14450145

申请日：2014-08-01

Applicant: Analog Devices Technology

Inventor： Abhijit Giri ,  Saurbh Srivastava ,  Michael S. Allen

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F2212/1024

Abstract: Digital signal processors often operate on two operands per instruction, and it is desirable to retrieve both operands in one cycle. Some data caches connect to the processor over two busses and internally uses two or more memory banks to store cache lines. The allocation of cache lines to specific banks is based on the address that the cache line is associated. When two memory accesses map to the same memory bank, fetching the operands incurs extra latency because the accesses are serialized. An improved bank organization for providing conflict-free dual-data cache access—a bus-based data cache system having two data buses and two memory banks—is disclosed. Each memory bank works as a default memory bank for the corresponding data bus. As long as the two values of data being accessed belong to two separate data sets assigned to the two respective data buses, memory bank conflicts are avoided.

Abstract translation: 数字信号处理器通常在每个指令的两个操作数上操作，并且期望在一个周期内检索两个操作数。 一些数据高速缓存通过两个总线连接到处理器，并且内部使用两个或多个存储体来存储高速缓存行。 将高速缓存行分配给特定存储区基于高速缓存行关联的地址。 当两个内存访问映射到同一个存储区时，获取操作数会导致额外的延迟，因为访问是序列化的。 公开了一种用于提供无冲突双数据高速缓存访​​问的改进的银行组织 - 具有两个数据总线和两个存储体的基于总线的数据高速缓存系统。 每个存储体都作为相应数据总线的默认存储体。 只要访问的数据的两个值属于分配给两个相应的数据总线的两个单独的数据集，就避免了存储体冲突。

公开(公告)号：US09092429B2

公开(公告)日：2015-07-28

申请号：US14040367

申请日：2013-09-27

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Michael S. Allen ,  John L. Redford

IPC: G06F3/06 ,  G06F13/28 ,  G06F13/38

CPC classification number: G06F13/28

Abstract: According to one example embodiment, a direct memory access (DMA) engine and buffer is disclosed. The vector buffer may be explicitly programmable, and may include advanced logic for reordering non-unity-stride vector data. An example MEMCPY instruction may provide an access request to the DMA buffer, which may then service the request asynchronously. Bitwise guards are set over memory in use, and cleared as each bit is read.

Abstract translation: 根据一个示例实施例，公开了直接存储器存取（DMA）引擎和缓冲器。 向量缓冲器可以是可显式可编程的，并且可以包括用于重新排序非单位步幅矢量数据的高级逻辑。 示例MEMCPY指令可以向DMA缓冲器提供访问请求，其可以异步地服务请求。 按位保护设置在使用中的内存中，并在读取每个位时清零。

公开(公告)号：US20140115302A1

公开(公告)日：2014-04-24

申请号：US13963793

申请日：2013-08-09

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Boris Lemer ,  Kaushal Sanghai ,  Michael G. Perkins ,  John L. Redford ,  Michael S. Allen

IPC: G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3887

Abstract: According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Abstract translation: 根据示例性实施例，诸如数字信号处理器（DSP）的处理器被提供有用作谓词计数器的寄存器。 谓词计数器可以包括两个有用的值，并且除了用作执行指令的条件之外，还可以跟踪循环或条件分支内的嵌套级别。 在某些情况下，谓词计数器可以被配置为在单指令，多数据（SIMD）模式或SIMD-在寄存器（SWAR）模式下操作。