公开(公告)号：US20140281435A1

公开(公告)日：2014-09-18

申请号：US14200788

申请日：2014-03-07

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Michael G. Perkins ,  John L. Redford ,  Kaushal Sanghai

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F8/4452 ,  G06F9/3836 ,  G06F9/3887

Abstract: In one particular example, this disclosure provides an efficient mechanism to determine the degree of parallelization possible for a loop in the presence of possible memory aliases that cannot be resolved at compile-time. Hardware instructions are provided that test memory addresses at run-time and set a mode or register that enables a single instance of a loop to run the maximum number of SIMD (Single Instruction, Multiple Data) lanes to run in parallel that obey the semantics of the original scalar loop. Other hardware features that extend applicability or performance of such instructions are enumerated.

Abstract translation: 在一个特定示例中，本公开提供了一种有效的机制，用于确定在编译时无法解析的可能存储器别名存在的循环可能的并行化程度。 提供了硬件指令，用于在运行时测试存储器地址，并设置一个模式或寄存器，该模式或寄存器使循环的单个实例运行最大数量的SIMD（单指令，多数据）通道并行运行，从而遵循语义 原始标量循环。 列举了扩展这些指令的适用性或性能的其他硬件功能。

公开(公告)号：US20140115302A1

公开(公告)日：2014-04-24

申请号：US13963793

申请日：2013-08-09

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Boris Lemer ,  Kaushal Sanghai ,  Michael G. Perkins ,  John L. Redford ,  Michael S. Allen

IPC: G06F9/30

CPC classification number: G06F9/30072 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3887

Abstract: According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Abstract translation: 根据示例性实施例，诸如数字信号处理器（DSP）的处理器被提供有用作谓词计数器的寄存器。 谓词计数器可以包括两个有用的值，并且除了用作执行指令的条件之外，还可以跟踪循环或条件分支内的嵌套级别。 在某些情况下，谓词计数器可以被配置为在单指令，多数据（SIMD）模式或SIMD-在寄存器（SWAR）模式下操作。

公开(公告)号：US09460016B2

公开(公告)日：2016-10-04

申请号：US14306162

申请日：2014-06-16

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： John L. Redford ,  Michael G. Perkins

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/0895 ,  Y02D10/13

Abstract: In an example, a system and method are provided for predicting in which way a requested memory address is most likely to be held in a multi-way cache, based on the last way accessed by the specified address register if available. If not available, then the system may determine that no best prediction is available. In that case, each way is read, and the superfluous values are disregarded, or a cache fill is performed as necessary. In certain embodiments, only a portion of the least significant bits of an add operation are used for way prediction in base-plus-offset addressing modes. This enables the decision to be made before the full-width add is complete, so that the clock cycle length is not unnecessarily lengthened by the prediction operation.

Abstract translation: 在一个示例中，提供了一种系统和方法，用于基于由指定地址寄存器访问的最后方式（如果可用）来预测所请求的存储器地址最有可能保持在多路高速缓存中的方式。 如果不可用，则系统可以确定没有可用的最佳预测。 在这种情况下，读取每种方式，忽略多余的值，或者根据需要执行缓存填充。 在某些实施例中，只有加法运算的最低有效位的一部分用于基加 - 偏移寻址模式中的方式预测。 这使得能够在全宽加法完成之前进行判定，从而通过预测操作不会不必要地延长时钟周期长度。

公开(公告)号：US10241793B2

公开(公告)日：2019-03-26

申请号：US14200788

申请日：2014-03-07

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Michael G. Perkins ,  John L. Redford ,  Kaushal Sanghai

IPC: G06F9/30 ,  G06F9/38 ,  G06F8/41

Abstract: In one particular example, this disclosure provides an efficient mechanism to determine the degree of parallelization possible for a loop in the presence of possible memory aliases that cannot be resolved at compile-time. Hardware instructions are provided that test memory addresses at run-time and set a mode or register that enables a single instance of a loop to run the maximum number of SIMD (Single Instruction, Multiple Data) lanes to run in parallel that obey the semantics of the original scalar loop. Other hardware features that extend applicability or performance of such instructions are enumerated.

公开(公告)号：US09342306B2

公开(公告)日：2016-05-17

申请号：US13963793

申请日：2013-08-09

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Boris Lerner ,  Kaushal Sanghai ,  Michael G. Perkins ,  John L. Redford ,  Michael S. Allen

IPC: G06F9/44 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30072 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3887

Abstract: According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Abstract translation: 根据示例性实施例，诸如数字信号处理器（DSP）的处理器被提供有用作谓词计数器的寄存器。 谓词计数器可以包括两个有用的值，并且除了用作执行指令的条件之外，还可以跟踪循环或条件分支中的嵌套级别。 在某些情况下，谓词计数器可以被配置为在单指令，多数据（SIMD）模式或SIMD-在寄存器（SWAR）模式下操作。