公开(公告)号：US09342306B2

公开(公告)日：2016-05-17

申请号：US13963793

申请日：2013-08-09

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andrew J. Higham ,  Boris Lerner ,  Kaushal Sanghai ,  Michael G. Perkins ,  John L. Redford ,  Michael S. Allen

IPC: G06F9/44 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30072 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3887

Abstract: According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep track of nesting levels within a loop or conditional branch. In some cases, the predicate counter may be configured to operate in single-instruction, multiple data (SIMD) mode, or SIMD-within-a-register (SWAR) mode.

Abstract translation: 根据示例性实施例，诸如数字信号处理器（DSP）的处理器被提供有用作谓词计数器的寄存器。 谓词计数器可以包括两个有用的值，并且除了用作执行指令的条件之外，还可以跟踪循环或条件分支中的嵌套级别。 在某些情况下，谓词计数器可以被配置为在单指令，多数据（SIMD）模式或SIMD-在寄存器（SWAR）模式下操作。

公开(公告)号：US08766992B2

公开(公告)日：2014-07-01

申请号：US13892508

申请日：2013-05-13

Applicant: Analog Devices Technology

Inventor： Boris Lerner ,  Michael Meyer-Pundsack ,  Gopal Gudhur Karanam ,  Pradip Thaker

IPC: G06F13/372 ,  G06K9/36 ,  G06K9/64 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract translation: 本发明的实施例提供了二维图像处理中的改进的定时控制，以便即使当处理操作转换到新的像素或新的像素帧时，仍然保持恒定的存储器读取速率和像素输出。 保持输入像素速率和输出像素速率之间的一对一关系，而不需要额外的时钟周期或存储器带宽，因为根据本发明的改进的定时控制通过预取一个新的像素数据列来利用空闲存储器带宽 在下一行或帧的第一像素块中，而当前行上的边缘像素块的新列被复制或清零。 当处理当前行上的边缘像素块时，下一行或帧的第一像素块中的数据就可以在没有额外的时钟周期或额外的存储器带宽的情况下进行计算。

公开(公告)号：US20130342551A1

公开(公告)日：2013-12-26

申请号：US13892531

申请日：2013-05-13

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Boris Lerner ,  Michael Meyer-Pundsack ,  Gopal Gudhur Karanam ,  Pradip Thaker

IPC: G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

公开(公告)号：US20130249923A1

公开(公告)日：2013-09-26

申请号：US13892508

申请日：2013-05-13

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Michael Meyer-Pundsack ,  Boris Lerner ,  Gopal Gudhur Karanam ,  Pradip Thacker

IPC: G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract translation: 本发明的实施例提供了二维图像处理中的改进的定时控制，以便即使当处理操作转换到新的像素或新的像素帧时，仍然保持恒定的存储器读取速率和像素输出。 保持输入像素速率和输出像素速率之间的一对一关系，而不需要额外的时钟周期或存储器带宽，因为根据本发明的改进的定时控制通过预取一个新的像素数据列来利用空闲存储器带宽 在下一行或帧的第一像素块中，而当前行上的边缘像素块的新列被复制或清零。 当处理当前行上的边缘像素块时，下一行或帧的第一像素块中的数据就可以在没有额外的时钟周期或额外的存储器带宽的情况下进行计算。

公开(公告)号：US08947446B2

公开(公告)日：2015-02-03

申请号：US13892531

申请日：2013-05-13

Applicant: Analog Devices Technology

Inventor： Boris Lerner ,  Michael Meyer-Pundsack ,  Gopal Gudhur Karanam ,  Pradip Thacker

IPC: G06F13/372 ,  G06K9/36 ,  G06K9/64 ,  G06T1/60 ,  G09G5/00 ,  G09G5/36 ,  G09G5/39

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Abstract translation: 本发明的实施例提供了二维图像处理中的改进的定时控制，即使当处理操作转换到新的像素像素或一行像素时，仍然保持恒定的提取速率和像素输出。 保持输入像素速率和输出像素速率之间的一对一关系，而不需要额外的时钟周期或存储器带宽，因为根据本发明的改进的定时控制通过预取一个新的像素数据列来利用空闲存储器带宽 在下一行或帧的第一像素块中，而当前行上的边缘像素块的新列被复制或清零。 当处理当前行上的边缘像素块时，下一行或帧的第一像素块中的数据就可以在没有额外的时钟周期或额外的存储器带宽的情况下进行计算。